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FLEX 10K
(R)
Embedded Programmable Logic Family
Data Sheet
May 1998, ver. 3.10
Features...
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The industryOs first embedded programmable logic device (PLD) family, providing system integration in a single device Embedded array for implementing megafunctions, such as efficient memory and specialized logic functions Logic array for general logic functions High density 10,000 to 250,000 typical gates (see Tables 1 and 2) Up to 40,960 RAM bits; 2,048 bits per embedded array block (EAB), all of which can be used without reducing logic capacity System-level features MultiVolt I/O interface support 5.0-V tolerant input pins in FLEX 10KA devices Low power consumption (typical specification less than 0.5 mA in standby mode for most devices) FLEX 10K and FLEX 10KA devices support peripheral component interconnect Special Interest GroupOs (PCI-SIG) PCI Local Bus Specification, Revision 2.1 FLEX 10KA devices include pull-up clamping diode, selectable on a pin-by-pin basis for 3.3-V PCI compliance Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990, available without consuming any device logic
Table 1. FLEX 10K Device Features
Feature
Typical gates (logic and RAM), Note (1) Usable gates Logic elements (LEs) Logic array blocks (LABs) Embedded array blocks (EABs) Total RAM bits Maximum user I/O pins
EPF10K10 EPF10K10A
10,000 7,000 to 31,000 576 72 3 6,144 134
EPF10K20
20,000 15,000 to 63,000 1,152 144 6 12,288 189
EPF10K30 EPF10K30A
30,000 22,000 to 69,000 1,728 216 6 12,288 246
EPF10K40
40,000 29,000 to 93,000 2,304 288 8 16,384 189
EPF10K50 EPF10K50V
50,000 36,000 to 116,000 2,880 360 10 20,480 310
Altera Corporation
A-DS-F10K-03.10
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FLEX 10K Embedded Programmable Logic Family Data Sheet
Table 2. FLEX 10K Device Features
Feature
Typical gates (logic and RAM), Note (1) Usable gates LEs LABs EABs Total RAM bits Maximum user I/O pins Note to tables:
(1) For designs that require JTAG boundary-scan testing, the built-in JTAG circuitry contributes up to 31,250 additional gates.
EPF10K70
70,000
EPF10K100 EPF10K100A
100,000
EPF10K130V
130,000
EPF10K250A
250,000 149,000 to 310,000 12,160 1,520 20 40,960 470
46,000 to 118,000 62,000 to 158,000 82,000 to 211,000 3,744 468 9 18,432 358 4,992 624 12 24,576 406 6,656 832 16 32,768 470
...and More Features

Devices are fabricated on advanced processes and operate with a 3.3- or 5.0-V supply voltage (see Table 3) In-circuit reconfigurability (ICR) via external Configuration EPROM, intelligent controller, or JTAG port ClockLock and ClockBoost options for reduced clock delay/skew and clock multiplication Built-in low-skew clock distribution trees 100% functional testing of all devices; test vectors or scan chains are not required
Table 3. Supply Voltages
Feature FLEX 10K Devices
EPF10K10 EPF10K20 EPF10K30 EPF10K40 EPF10K50 EPF10K70 EPF10K100 Supply voltage (VCCINT) 5.0 V
FLEX 10KA Devices
EPF10K10A EPF10K30A EPF10K50V EPF10K100A EPF10K130V EPF10K250A 3.3 V
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Altera Corporation
FLEX 10K Embedded Programmable Logic Family Data Sheet s
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Flexible interconnect FastTrack Interconnect continuous routing structure for fast, predictable interconnect delays Dedicated carry chain that implements arithmetic functions such as fast adders, counters, and comparators (automatically used by software tools and megafunctions) Dedicated cascade chain that implements high-speed, high-fanin logic functions (automatically used by software tools and megafunctions) Tri-state emulation that implements internal tri-state buses Up to six global clock signals and four global clear signals Powerful I/O pins Individual tri-state output enable control for each pin Open-drain option on each I/O pin Programmable output slew-rate control to reduce switching noise Peripheral register for fast setup and clock-to-output delay Flexible package options Available in a variety of packages with 84 to 600 pins (see Table 4) Pin-compatibility with other FLEX 10K devices in the same package Software design support and automatic place-and-route provided by AlteraOs MAX+PLUS II development system for 486- and Pentiumbased PCs and Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC System/6000 workstations Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), DesignWare components, Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, VeriBest, and Viewlogic
Altera Corporation
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FLEX 10K Embedded Programmable Logic Family Data Sheet
Table 4. FLEX 10K Package Options & I/O Pin Count
Device
Notes (1), (2)
84-Pin 144-Pin 208-Pin 240-Pin 256-Pin 356-Pin 403-Pin 503-Pin 599-Pin 600-Pin PLCC TQFP PQFP PQFP BGA BGA PGA PGA PGA BGA RQFP RQFP
59 102 102 102 102 134 134 147 147 147 147 189 189 189 189 189 189 189 189 274 470 470 274 274 358 406 406 470 470 310 189 246
EPF10K10 EPF10K10A EPF10K20 EPF10K30 EPF10K30A EPF10K40 EPF10K50 EPF10K50V EPF10K70 EPF10K100 EPF10K100A EPF10K130V EPF10K250A Notes:
(1) (2)
Contact Altera Customer Marketing for up-to-date information on package availability. FLEX 10K device package types include plastic J-lead chip carrier (PLCC), thin quad flat pack (TQFP), plastic quad flat pack (PQFP), power quad flat pack (RQFP), ball-grid array (BGA), and pin-grid array (PGA) packages.
General Description
AlteraOs FLEX 10K devices are the industryOs first embedded PLDs. Based on reconfigurable CMOS SRAM elements, the Flexible Logic Element MatriX (FLEX) architecture incorporates all features necessary to implement common gate array megafunctions. With up to 250,000 gates, the FLEX 10K family provides the density, speed, and features to integrate entire systems, including multiple 32-bit buses, into a single device. FLEX 10K devices are configurable, and they are 100% tested prior to shipment. As a result, the designer is not required to generate test vectors for fault coverage purposes. Instead, the designer can focus on simulation and design verification. In addition, the designer does not need to manage inventories of different gate array designs; FLEX 10K devices can be configured on the board for the specific functionality required. Table 5 shows FLEX 10K performance for some common designs. All performance values shown were obtained with Synopsys DesignWare or LPM functions. No special design technique is required to implement the applications; the designer simply infers or instantiates a function in a Verilog HDL, VHDL, Altera Hardware Description Language (AHDL), or schematic design file.
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Altera Corporation
FLEX 10K Embedded Programmable Logic Family Data Sheet
Table 5. FLEX 10K Performance
Application Resources Used LEs
16-bit loadable counter, Note (1) 16-bit accumulator, Note (1) 16-to-1 multiplexer, Note (2) 256 x 8 RAM read cycle speed, Note (3) 256 x 8 RAM write cycle speed, Note (3) Notes:
(1) (2) (3) The speed grade of this application is limited because of clock high and low specifications. This application uses combinatorial inputs and outputs. This application uses registered inputs and outputs.
Performance
Units
EABs -1 Speed Grade -2 Speed Grade -3 Speed Grade -4 Speed Grade
0 0 0 1 1 204 204 4.5 185 106 166 166 5.8 118 86 125 125 6.0 103 77 95 95 7.0 84 63 MHz MHz ns MHz MHz
16 16 10 0 0
The FLEX 10K architecture is similar to that of embedded gate arrays, the fastest-growing segment of the gate array market. As with standard gate arrays, embedded gate arrays implement general logic in a conventional Osea-of-gatesO architecture. In addition, embedded gate arrays have dedicated die areas for implementing large, specialized functions. By embedding functions in silicon, embedded gate arrays provide reduced die area and increased speed compared to standard gate arrays. However, embedded megafunctions typically cannot be customized, limiting the designerOs options. In contrast, FLEX 10K devices are programmable, providing the designer with full control over embedded megafunctions and general logic while facilitating iterative design changes during debugging. Each FLEX 10K device contains an embedded array and a logic array. The embedded array is used to implement a variety of memory functions or complex logic functions, such as digital signal processing (DSP), microcontroller, wide-data-path manipulation, and data-transformation functions. The logic array performs the same function as the sea-of-gates in the gate array: it is used to implement general logic, such as counters, adders, state machines, and multiplexers. The combination of embedded and logic arrays provides the high performance and high density of embedded gate arrays, enabling designers to implement an entire system on a single device.
Altera Corporation
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FLEX 10K Embedded Programmable Logic Family Data Sheet
FLEX 10K devices are configured at system power-up with data stored in an Altera serial Configuration EPROM device or provided by a system controller. Altera offers the EPC1 and EPC1441 Configuration EPROMs, which configure FLEX 10K devices via a serial data stream. Configuration data can also be downloaded from system RAM or from AlteraOs BitBlaster serial download cable, ByteBlaster parallel port download cable, or ByteBlasterMV parallel port download cable. After a FLEX 10K device has been configured, it can be reconfigured in-circuit by resetting the device and loading new data. Because reconfiguration requires less than 320 ms, real-time changes can be made during system operation. FLEX 10K devices contain an optimized interface that permits microprocessors to configure FLEX 10K devices serially or in parallel, and synchronously or asynchronously. The interface also enables microprocessors to treat a FLEX 10K device as memory and configure the device by writing to a virtual memory location, making it very easy for the designer to reconfigure the device.
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Go to the Configuration EPROMs for FLEX Devices Data Sheet, BitBlaster Serial Download Cable Data Sheet, ByteBlaster Parallel Port Download Cable Data Sheet, ByteBlasterMV Parallel Port Download Cable Data Sheet, and AN 59 (Configuring FLEX 10K Devices) for more information. FLEX 10K devices are supported by AlteraOs MAX+PLUS II development system, a single, integrated package that offers schematic, textNincluding AHDLNand waveform design entry; compilation and logic synthesis; full simulation and worst-case timing analysis; and device configuration. The MAX+PLUS II software provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other interfaces for additional design entry and simulation support from other industry-standard PC- and UNIX workstation-based EDA tools. The MAX+PLUS II software interfaces easily with common gate array EDA tools for synthesis and simulation. For example, the MAX+PLUS II software can generate Verilog HDL files for simulation with tools such as Cadence Verilog-XL. Additionally, the MAX+PLUS II software contains EDA libraries that use device-specific features such as carry chains, which are used for fast counter and arithmetic functions. For instance, the Synopsys Design Compiler library supplied with the MAX+PLUS II development system includes DesignWare functions that are optimized for the FLEX 10K architecture. The MAX+PLUS II software runs on 486- and Pentium-based PCs, and Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC System/6000 workstations.
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Go to the MAX+PLUS II Programmable Logic Development System & Software Data Sheet in this data book for more information.
Altera Corporation
FLEX 10K Embedded Programmable Logic Family Data Sheet
Functional Description
Each FLEX 10K device contains an embedded array to implement memory and specialized logic functions, and a logic array to implement general logic. The embedded array consists of a series of EABs. When implementing memory functions, each EAB provides 2,048 bits, which can be used to create RAM, ROM, dual-port RAM, or first-in first-out (FIFO) functions. When implementing logic, each EAB can contribute 100 to 600 gates towards complex logic functions, such as multipliers, microcontrollers, state machines, and DSP functions. EABs can be used independently, or multiple EABs can be combined to implement larger functions. The logic array consists of logic array blocks (LABs). Each LAB contains eight LEs and a local interconnect. An LE consists of a 4-input look-up table (LUT), a programmable flipflop, and dedicated signal paths for carry and cascade functions. The eight LEs can be used to create medium-sized blocks of logicNsuch as 8-bit counters, address decoders, or state machinesNor combined across LABs to create larger logic blocks. Each LAB represents about 96 usable gates of logic. Signal interconnections within FLEX 10K devices and to and from device pins are provided by the FastTrack Interconnect, a series of fast, continuous row and column channels that run the entire length and width of the device. Each I/O pin is fed by an I/O element (IOE) located at the end of each row and column of the FastTrack Interconnect. Each IOE contains a bidirectional I/O buffer and a flipflop that can be used as either an output or input register to feed input, output, or bidirectional signals. When used with a dedicated clock pin, these registers provide exceptional performance. As inputs, they provide setup times of as low as 3.7 ns and hold times of 0 ns; as outputs, these registers provide clock-to-output times as low as 5.3 ns. IOEs provide a variety of features, such as JTAG BST support, slew-rate control, tri-state buffers, and open-drain outputs. Figure 1 shows a block diagram of the FLEX 10K architecture. Each group of LEs is combined into an LAB; LABs are arranged into rows and columns. Each row also contains a single EAB. The LABs and EABs are interconnected by the FastTrack Interconnect. IOEs are located at the end of each row and column of the FastTrack Interconnect.
Altera Corporation
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FLEX 10K Embedded Programmable Logic Family Data Sheet
Figure 1. FLEX 10K Device Block Diagram
Embedded Array Block (EAB) I/O Element (IOE)
IOE IOE IOE IOE IOE IOE IOE IOE IOE IOE
IOE
IOE
IOE
IOE
Column Interconnect
Logic Array
EAB
Logic Array Block (LAB)
IOE
IOE
IOE
IOE
Logic Element (LE) Row Interconnect
EAB
Local Interconnect Logic Array
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
Embedded Array
FLEX 10K devices provide six dedicated inputs that drive the control inputs of the flipflops to ensure the efficient distribution of high-speed, low-skew (less than 1.5 ns) control signals. These signals use dedicated routing channels that provide shorter delays and lower skews than the FastTrack Interconnect. Four of the dedicated inputs drive four global signals. These four global signals can also be driven by internal logic, providing an ideal solution for a clock divider or an internally generated asynchronous clear signal that clears many registers in the device.
Embedded Array Block
The EAB is a flexible block of RAM with registers on the input and output ports, and is used to implement common gate array megafunctions. The EAB is also suitable for functions such as multipliers, vector scalars, and error correction circuits, because it is large and flexible. These functions can be combined in applications such as digital filters and microcontrollers.
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Altera Corporation
FLEX 10K Embedded Programmable Logic Family Data Sheet
Logic functions are implemented by programming the EAB with a readonly pattern during configuration, creating a large LUT. With LUTs, combinatorial functions are implemented by looking up the results, rather than by computing them. This implementation of combinatorial functions can be faster than using algorithms implemented in general logic, a performance advantage that is further enhanced by the fast access times of EABs. The large capacity of EABs enables designers to implement complex functions in one logic level without the routing delays associated with linked LEs or field-programmable gate array (FPGA) RAM blocks. For example, a single EAB can implement a 4 x 4 multiplier with eight inputs and eight outputs. Parameterized functions such as LPM functions can automatically take advantage of the EAB. The EAB provides advantages over FPGAs, which implement on-board RAM as arrays of small, distributed RAM blocks. These FPGA RAM blocks contain delays that are less predictable as the size of the RAM increases. In addition, FPGA RAM blocks are prone to routing problems because small blocks of RAM must be connected together to make larger blocks. In contrast, EABs can be used to implement large, dedicated blocks of RAM that eliminate these timing and routing concerns. EABs can be used to implement synchronous RAM, which is easier to use than asynchronous RAM. A circuit using asynchronous RAM must generate the RAM write enable (WE) signal, while ensuring that its data and address signals meet setup and hold time specifications relative to the WE signal. In contrast, the EABOs synchronous RAM generates its own WE signal and is self-timed with respect to the global clock. A circuit using the EABOs self-timed RAM need only meet the setup and hold time specifications of the global clock. When used as RAM, each EAB can be configured in any of the following sizes: 256 x 8, 512 x 4, 1,024 x 2, or 2,048 x 1. See Figure 2.
Figure 2. EAB Memory Configurations
256 x 8
512 x 4
1,024 x 2
2,048 x 1
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FLEX 10K Embedded Programmable Logic Family Data Sheet
Larger blocks of RAM are created by combining multiple EABs. For example, two 256 x 8 RAM blocks can be combined to form a 256 x 16 RAM block; two 512 x 4 blocks of RAM can be combined to form a 512 x 8 RAM block. See Figure 3.
Figure 3. Examples of Combining EABs
256 x 16 256 x 8 512 x 4 512 x 8
256 x 8 512 x 4
If necessary, all EABs in a device can be cascaded to form a single RAM block. EABs can be cascaded to form RAM blocks of up to 2,048 words without impacting timing. AlteraOs MAX+PLUS II software automatically combines EABs to meet a designerOs RAM specifications. EABs provide flexible options for driving and controlling clock signals. Different clocks can be used for the EAB inputs and outputs. Registers can be independently inserted on the data input, EAB output, or the address and WE signals. The global signals and the EAB local interconnect can drive the WE signal. The global signals, dedicated clock pins, and EAB local interconnect can drive the EAB clock signals. Because the LEs drive the EAB local interconnect, the LEs can control the WE signal or the EAB clock signals. Each EAB is fed by a row interconnect and can drive out to row and column interconnects. Each EAB output can drive up to two row channels and up to two column channels; the unused row channel can be driven by other LEs. This feature increases the routing resources available for EAB outputs. See Figure 4.
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Altera Corporation
FLEX 10K Embedded Programmable Logic Family Data Sheet
Figure 4. FLEX 10K Embedded Array Block
Dedicated Inputs & Global Signals Chip-Wide Reset
Row Interconnect
Note (1)
6
2, 4, 8, 16
D 8, 4, 2, 1
Q
Data In
Data Out
D
Q
24
2, 4, 8, 16 Address D 8, 9, 10, 11 Q
RAM/ROM 256 x 8 512 x 4 1,024 x 2 2,048 x 1
WE D Q
Column Interconnect
EAB Local Interconnect, Note (1)
Note:
(1) EPF10K10, EPF10K10A, EPF10K20, EPF10K30, EPF10K30A, EPF10K40, EPF10K50, and EPF10K50V devices have 22 EAB local interconnect channels; EPF10K70, EPF10K100, EPF10K100A, EPF10K130V, and EPF10K250A devices have 26.
Altera Corporation
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FLEX 10K Embedded Programmable Logic Family Data Sheet
Logic Array Block
The LAB consists of eight LEs, their associated carry and cascade chains, LAB control signals, and the LAB local interconnect. The LAB provides the coarse-grained structure to the FLEX 10K architecture, facilitating efficient routing with optimum device utilization and high performance. See Figure 5.
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Altera Corporation
FLEX 10K Embedded Programmable Logic Family Data Sheet
Figure 5. FLEX 10K LAB
Dedicated Inputs & Global Signals
Row Interconnect
Note (1) LAB Local Interconnect Note (2) LAB Control Signals
4 4 4 4 4 4 4 4 4
6 16 Carry-In & Cascade-In 2 LE1 LE2 LE3 8 LE4 LE5 LE6 LE7 LE8 16 4
See Figure 11 for details.
8
24
4
Column-to-Row Interconnect
Column Interconnect
8
2
Carry-Out & Cascade-Out
Notes:
(1) EPF10K10, EPF10K10A, EPF10K20, EPF10K30, EPF10K30A, EPF10K40, EPF10K50, and EPF10K50V devices have 22 inputs to the LAB local interconnect channel from the row; EPF10K70, EPF10K100, EPF10K100A, EPF10K130V, and EPF10K250A devices have 26. EPF10K10, EPF10K10A, EPF10K20, EPF10K30, EPF10K30A, EPF10K40, EPF10K50, EPF10K50, and EPF10K50V devices have 30 LAB local interconnect channels; EPF10K70, EPF10K100, EPF10K100A, EPF10K130V, and EPF10K250A devices have 34.
(2)
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FLEX 10K Embedded Programmable Logic Family Data Sheet
Each LAB provides four control signals with programmable inversion that can be used in all eight LEs. Two of these signals can be used as clocks; the other two can be used for clear/preset control. The LAB clocks can be driven by the dedicated clock input pins, global signals, I/O signals, or internal signals via the LAB local interconnect. The LAB preset and clear control signals can be driven by the global signals, I/O signals, or internal signals via the LAB local interconnect. The global control signals are typically used for global clock, clear, or preset signals because they provide asynchronous control with very low skew across the device. If logic is required on a control signal, it can be generated in one or more LEs in any LAB and driven into the local interconnect of the target LAB. In addition, the global control signals can be generated from LE outputs.
Logic Element
The LE, the smallest unit of logic in the FLEX 10K architecture, has a compact size that provides efficient logic utilization. Each LE contains a four-input LUT, which is a function generator that can quickly compute any function of four variables. In addition, each LE contains a programmable flipflop with a synchronous enable, a carry chain, and a cascade chain. Each LE drives both the local and the FastTrack Interconnect. See Figure 6.
Figure 6. FLEX 10K Logic Element
Carry-In Cascade-In
Register Bypass
Programmable Register
DATA1 DATA2 DATA3 DATA4
Look-Up Table (LUT)
Carry Chain
Cascade Chain
D
PRN Q
to FastTrack Interconnect
ENA CLRN to LAB Local Interconnect
LABCTRL1 LABCTRL2 Chip-Wide Reset
Clear/ Preset Logic
Clock Select LABCTRL3 LABCTRL4 Carry-Out Cascade-Out
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Altera Corporation
FLEX 10K Embedded Programmable Logic Family Data Sheet
The programmable flipflop in the LE can be configured for D, T, JK, or SR operation. The clock, clear, and preset control signals on the flipflop can be driven by global signals, general-purpose I/O pins, or any internal logic. For combinatorial functions, the flipflop is bypassed and the output of the LUT drives the output of the LE. The LE has two outputs that drive the interconnect; one drives the local interconnect and the other drives either the row or column FastTrack Interconnect. The two outputs can be controlled independently; for example, the LUT can drive one output while the register drives the other output. This feature, called register packing, can improve LE utilization because the register and the LUT can be used for unrelated functions. The FLEX 10K architecture provides two types of dedicated high-speed data paths that connect adjacent LEs without using local interconnect paths: carry chains and cascade chains. The carry chain supports highspeed counters and adders; the cascade chain implements wide-input functions with minimum delay. Carry and cascade chains connect all LEs in an LAB and all LABs in the same row. Intensive use of carry and cascade chains can reduce routing flexibility. Therefore, the use of these chains should be limited to speed-critical portions of a design.
Carry Chain
The carry chain provides a very fast (as low as 0.2 ns) carry-forward function between LEs. The carry-in signal from a lower-order bit drives forward into the higher-order bit via the carry chain, and feeds into both the LUT and the next portion of the carry chain. This feature allows the FLEX 10K architecture to implement high-speed counters, adders, and comparators of arbitrary width efficiently. Carry chain logic can be created automatically by the MAX+PLUS II Compiler during design processing, or manually by the designer during design entry. Parameterized functions such as LPM and DesignWare functions automatically take advantage of carry chains. Carry chains longer than eight LEs are automatically implemented by linking LABs together. For enhanced fitting, a long carry chain skips alternate LABs in a row. A carry chain longer than one LAB skips either from even-numbered LAB to even-numbered LAB, or from oddnumbered LAB to odd-numbered LAB. For example, the last LE of the first LAB in a row carries to the first LE of the third LAB in the row. The carry chain does not cross the EAB at the middle of the row. For instance, in the EPF10K50 device, the carry chain stops at the eighteenth LAB and a new one begins at the nineteenth LAB.
Altera Corporation
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FLEX 10K Embedded Programmable Logic Family Data Sheet
Figure 7 shows how an n-bit full adder can be implemented in n + 1 LEs with the carry chain. One portion of the LUT generates the sum of two bits using the input signals and the carry-in signal; the sum is routed to the output of the LE. The register can be bypassed for simple adders, but can be used for an accumulator function. Another portion of the LUT and the carry chain logic generate the carry-out signal, which is routed directly to the carry-in signal of the next-higher-order bit. The final carry-out signal is routed to an LE, where it can be used as a general-purpose signal.
Figure 7. Carry Chain Operation (n-bit Full Adder)
Carry-In
a1 b1
LUT
Register
s1
Carry Chain LE1
a2 b2
LUT
Register
s2
Carry Chain LE2
an bn
LUT
Register
sn
Carry Chain LEn
LUT
Register
Carry-Out
Carry Chain LEn + 1
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Altera Corporation
FLEX 10K Embedded Programmable Logic Family Data Sheet
Cascade Chain
With the cascade chain, the FLEX 10K architecture can implement functions that have a very wide fan-in. Adjacent LUTs can be used to compute portions of the function in parallel; the cascade chain serially connects the intermediate values. The cascade chain can use a logical AND or logical OR (via De MorganOs inversion) to connect the outputs of adjacent LEs. Each additional LE provides four more inputs to the effective width of a function, with a delay as low as 0.7 ns per LE. Cascade chain logic can be created automatically by the MAX+PLUS II Compiler during design processing, or manually by the designer during design entry. Cascade chains longer than eight bits are automatically implemented by linking several LABs together. For easier routing, a long cascade chain skips every other LAB in a row. A cascade chain longer than one LAB skips either from even-numbered LAB to even-numbered LAB, or from odd-numbered LAB to odd-numbered LAB (e.g., the last LE of the first LAB in a row cascades to the first LE of the third LAB.) The cascade chain does not cross the center of the row (e.g., in the EPF10K50 device, the cascade chain stops at the eighteenth LAB and a new one begins at the nineteenth LAB). This break is due to the EABOs placement in the middle of the row. Figure 8 shows how the cascade function can connect adjacent LEs to form functions with a wide fan-in. These examples show functions of 4n variables implemented with n LEs. The LE delay is as low as 1.9 ns; the cascade chain delay is as low as 0.7 ns. With the cascade chain, approximately 4.2 ns is needed to decode a 16-bit address.
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FLEX 10K Embedded Programmable Logic Family Data Sheet
Figure 8. Cascade Chain Operation
AND Cascade Chain OR Cascade Chain
d[3..0]
LUT LE1
d[3..0]
LUT LE1
d[7..4]
LUT LE2
d[7..4]
LUT LE2
d[(4n-1)..(4n-4)]
LUT LEn
d[(4n-1)..(4n-4)]
LUT LEn
LE Operating Modes
The FLEX 10K LE can operate in the following four modes:
s s s s
Normal mode Arithmetic mode Up/down counter mode Clearable counter mode
Each of these modes uses LE resources differently. In each mode, seven available inputs to the LENthe four data inputs from the LAB local interconnect, the feedback from the programmable register, and the carryin and cascade-in from the previous LENare directed to different destinations to implement the desired logic function. Three inputs to the LE provide clock, clear, and preset control for the register. The MAX+PLUS II software, in conjunction with parameterized functions such as LPM and DesignWare functions, automatically chooses the appropriate mode for common functions such as counters, adders, and multipliers. If required, the designer can also create special-purpose functions to use an LE operating mode for optimal performance. The architecture provides a synchronous clock enable to the register in all four modes. The MAX+PLUS II software can set DATA1 to enable the register synchronously, providing easy implementation of fully synchronous designs.
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FLEX 10K Embedded Programmable Logic Family Data Sheet
Figure 9 shows the LE operating modes.
Figure 9. FLEX 10K LE Operating Modes
Normal Mode
Carry-In DATA1 DATA2 DATA3 4-Input LUT D Cascade-In LE-Out to FastTrack Interconnect PRN Q LE-Out to Local Interconnect
ENA CLRN DATA4 Cascade-Out
Arithmetic Mode
Carry-In Cascade-In LE-Out DATA1 DATA2 PRN D Q ENA CLRN
3-Input LUT
3-Input LUT Carry-Out Cascade-Out
Up/Down Counter Mode
Carry-In Cascade-In
DATA1 (ena) DATA2 (u/d) DATA3 (data)
3-Input LUT
1 0
D
PRN Q
LE-Out
3-Input LUT DATA4 (nload) Carry-Out Cascade-Out
ENA CLRN
Clearable Counter Mode
Carry-In
DATA1 (ena) DATA2 (nclr) DATA3 (data)
3-Input LUT
1 0
D
PRN Q
LE-Out
3-Input LUT DATA4 (nload) Carry-Out Cascade-Out
ENA CLRN
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FLEX 10K Embedded Programmable Logic Family Data Sheet
Normal Mode The normal mode is suitable for general logic applications and wide decoding functions that can take advantage of a cascade chain. In normal mode, four data inputs from the LAB local interconnect and the carry-in are inputs to a 4-input LUT. The MAX+PLUS II Compiler automatically selects the carry-in or the DATA3 signal as one of the inputs to the LUT. The LUT output can be combined with the cascade-in signal to form a cascade chain through the cascade-out signal. Either the register or the LUT can be used to drive both the local interconnect and the FastTrack Interconnect at the same time. The LUT and the register in the LE can be used independently; this feature is known as register packing. To support register packing, the LE has two outputs; one drives the local interconnect and the other drives the FastTrack Interconnect. The DATA4 signal can drive the register directly, allowing the LUT to compute a function that is independent of the registered signal; a 3-input function can be computed in the LUT, and a fourth independent signal can be registered. Alternatively, a 4-input function can be generated, and one of the inputs to this function can be used to drive the register. The register in a packed LE can still use the clock enable, clear, and preset signals in the LE. In a packed LE, the register can drive the FastTrack Interconnect while the LUT drives the local interconnect, or vice versa. Arithmetic Mode The arithmetic mode offers two 3-input LUTs that are ideal for implementing adders, accumulators, and comparators. One LUT computes a 3-input function; the other generates a carry output. As shown in Figure 9 on page 19, the first LUT uses the carry-in signal and two data inputs from the LAB local interconnect to generate a combinatorial or registered output. For example, in an adder, this output is the sum of three signals: a, b, and carry-in. The second LUT uses the same three signals to generate a carry-out signal, thereby creating a carry chain. The arithmetic mode also supports simultaneous use of the cascade chain. Up/Down Counter Mode The up/down counter mode offers counter enable, clock enable, synchronous up/down control, and data loading options. These control signals are generated by the data inputs from the LAB local interconnect, the carry-in signal, and output feedback from the programmable register. Two 3-input LUTs are used: one generates the counter data, and the other generates the fast carry bit. A 2-to-1 multiplexer provides synchronous loading. Data can also be loaded asynchronously with the clear and preset register control signals, without using the LUT resources.
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FLEX 10K Embedded Programmable Logic Family Data Sheet
Clearable Counter Mode The clearable counter mode is similar to the up/down counter mode, but supports a synchronous clear instead of the up/down control. The clear function is substituted for the cascade-in signal in the up/down counter mode. Two 3-input LUTs are used: one generates the counter data, the other generates the fast carry bit. Synchronous loading is provided by a 2-to-1 multiplexer. The output of this multiplexer is ANDed with a synchronous clear signal.
Internal Tri-State Emulation
Internal tri-state emulation provides internal tri-stating without the limitations of a physical tri-state bus. In a physical tri-state bus, the tristate buffersO output enable (OE) signals select which signal drives the bus. However, if multiple OE signals are active, contending signals can be driven onto the bus. Conversely, if no OE signals are active, the bus will float. Internal tri-state emulation resolves contending tri-state buffers to a low value and floating buses to a high value, thereby eliminating these problems. The MAX+PLUS II software automatically implements tri-state bus functionality with a multiplexer.
Clear & Preset Logic Control
Logic for the programmable registerOs clear and preset functions is controlled by the DATA3, LABCTRL1, and LABCTRL2 inputs to the LE. The clear and preset control structure of the LE asynchronously loads signals into a register. Either LABCTRL1 or LABCTRL2 can control the asynchronous clear. Alternatively, the register can be set up so that LABCTRL1 implements an asynchronous load. The data to be loaded is driven to DATA3; when LABCTRL1 is asserted, DATA3 is loaded into the register. During compilation, the MAX+PLUS II Compiler automatically selects the best control signal implementation. Because the clear and preset functions are active-low, the Compiler automatically assigns a logic high to an unused clear or preset. The clear and preset logic is implemented in one of the following six modes chosen during design entry:
s s s s s s
Asynchronous clear Asynchronous preset Asynchronous clear and preset Asynchronous load with clear Asynchronous load with preset Asynchronous load without clear or preset
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FLEX 10K Embedded Programmable Logic Family Data Sheet
In addition to the six clear and preset modes, FLEX 10K devices provide a chip-wide reset pin that can reset all registers in the device. Use of this feature is set during design entry. In any of the clear and preset modes, the chip-wide reset overrides all other signals. Registers with asynchronous presets may be preset when the chip-wide reset is asserted. Inversion can be used to implement the asynchronous preset. Figure 10 shows examples of how to enter a design section for the desired functionality.
Figure 10. LE Clear & Preset Modes
Asynchronous Clear
VCC Chip-Wide Reset LABCTRL1 or LABCTRL 2 PRN Q LABCTRL2 Chip-Wide Reset
Asynchronous Preset
Asynchronous Preset & Clear
LABCTRL1 PRN Q
D
PRN Q
D
D LABCTRL1 or LABCTRL2 Chip-Wide Reset CLRN
CLRN
CLRN VCC
Asynchronous Load with Clear
NOT LABCTRL1 (Asynchronous Load) DATA3 (Data) NOT LABCTRL2 (Clear) Chip-Wide Reset D PRN Q
Asynchronous Load without Clear or Preset
NOT LABCTRL1 (Asynchronous Load) DATA3 (Data) D PRN Q
CLRN NOT
CLRN
Chip-Wide Reset
Asynchronous Load with Preset
NOT LABCTRL1 (Asynchronous Load) LABCTRL2 (Preset) D DATA3 (Data) NOT
PRN Q
CLRN
Chip-Wide Reset
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FLEX 10K Embedded Programmable Logic Family Data Sheet
Asynchronous Clear The flipflop can be cleared by either LABCTRL1 or LABCTRL2. In this mode, the preset signal is tied to VCC to deactivate it. Asynchronous Preset An asynchronous preset is implemented as either an asynchronous load, or with an asynchronous clear. If DATA3 is tied to VCC, asserting LABCTRL1 asynchronously loads a one into the register. Alternatively, the MAX+PLUS II software can provide preset control by using the clear and inverting the input and output of the register. Inversion control is available for the inputs to both LEs and IOEs. Therefore, if a register is preset by only one of the two LABCTRL signals, the DATA3 input is not needed and can be used for one of the LE operating modes. Asynchronous Preset & Clear When implementing asynchronous clear and preset, LABCTRL1 controls the preset and LABCTRL2 controls the clear. DATA3 is tied to VCC, therefore, asserting LABCTRL1 asynchronously loads a one into the register, effectively presetting the register. Asserting LABCTRL2 clears the register. Asynchronous Load with Clear When implementing an asynchronous load in conjunction with the clear, LABCTRL1 implements the asynchronous load of DATA3 by controlling the register preset and clear. LABCTRL2 implements the clear by controlling the register clear; LABCTRL2 does not have to feed the preset circuits. Asynchronous Load with Preset When implementing an asynchronous load in conjunction with preset, the MAX+PLUS II software provides preset control by using the clear and inverting the input and output of the register. Asserting LABCTRL2 presets the register, while asserting LABCTRL1 loads the register. The MAX+PLUS II software inverts the signal that drives DATA3 to account for the inversion of the registerOs output. Asynchronous Load without Preset or Clear When implementing an asynchronous load without preset or clear, LABCTRL1 implements the asynchronous load of DATA3 by controlling the register preset and clear.
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FLEX 10K Embedded Programmable Logic Family Data Sheet
FastTrack Interconnect
In the FLEX 10K architecture, connections between LEs and device I/O pins are provided by the FastTrack Interconnect, which is a series of continuous horizontal and vertical routing channels that traverse the device. This global routing structure provides predictable performance, even in complex designs. In contrast, the segmented routing in FPGAs requires switch matrices to connect a variable number of routing paths, increasing the delays between logic resources and reducing performance. The FastTrack Interconnect consists of row and column interconnect channels that span the entire device. Each row of LABs is served by a dedicated row interconnect. The row interconnect can drive I/O pins and feed other LABs in the device. The column interconnect routes signals between rows and can drive I/O pins. A row channel can be driven by an LE or by one of three column channels. These four signals feed dual 4-to-1 multiplexers that connect to two specific row channels. These multiplexers, which are connected to each LE, allow column channels to drive row channels even when all eight LEs in an LAB drive the row interconnect. Each column of LABs is served by a dedicated column interconnect. The column interconnect can then drive I/O pins or another rowOs interconnect to route the signals to other LABs in the device. A signal from the column interconnect, which can be either the output of an LE or an input from an I/O pin, must be routed to the row interconnect before it can enter an LAB or EAB. Each row channel that is driven by an IOE or EAB can drive one specific column channel. Access to row and column channels can be switched between LEs in adjacent pairs of LABs. For example, an LE in one LAB can drive the row and column channels normally driven by a particular LE in the adjacent LAB in the same row, and vice versa. This routing flexibility enables routing resources to be used more efficiently. See Figure 11.
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FLEX 10K Embedded Programmable Logic Family Data Sheet
Figure 11. LAB Connections to Row & Column Interconnect
Column Channels
Row Channels
to Other Columns
At each intersection, four row channels can drive column channels.
Each LE can drive two row channels.
from Adjacent LAB to Adjacent LAB LE 1
LE 2
Each LE can switch interconnect access with an LE in the adjacent LAB.
LE 8
to LAB Local Interconnect
to Other Rows
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FLEX 10K Embedded Programmable Logic Family Data Sheet
For improved routability, the row interconnect is comprised of a combination of full-length and half-length channels. The full-length channels connect to all LABs in a row; the half-length channels connect to the LABs in half of the row. The EAB can be driven by the half-length channels in the left half of the row and by the full-length channels. The EAB drives out to the full-length channels. In addition to providing a predictable, row-wide interconnect, this architecture provides increased routing resources. Two neighboring LABs can be connected using a halfrow channel, thereby saving the other half of the channel for the other half of the row. Table 6 summarizes the FastTrack Interconnect resources available in each FLEX 10K device.
Table 6. FLEX 10K FastTrack Interconnect Resources
Device
EPF10K10 EPF10K10A EPF10K20 EPF10K30 EPF10K30A EPF10K30E EPF10K40 EPF10K50 EPF10K50V EPF10K70 EPF10K100 EPF10K100A EPF10K130V EPF10K250A
Rows
3 6 6
Channels per Row
144 144 216
Columns
24 24 36
Channels per Column
24 24 24
8 10 9 12 16 20
216 216 312 312 312 456
36 36 52 52 52 76
24 24 24 24 32 40
In addition to general-purpose I/O pins, FLEX 10K devices have six dedicated input pins that provide low-skew signal distribution across the device. These six inputs can be used for global clock, clear, preset, and peripheral output enable and clock enable control signals. These signals are available as control signals for all LABs and IOEs in the device. The dedicated inputs can also be used as general-purpose data inputs because they can feed the local interconnect of each LAB in the device. However, the use of dedicated inputs as data inputs can introduce additional delay into the control signal network.
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FLEX 10K Embedded Programmable Logic Family Data Sheet
Figure 12 shows the interconnection of adjacent LABs and EABs, with row, column, and local interconnects, as well as the associated cascade and carry chains. Each LAB is labeled according to its location: a letter represents the row and a number represents the column. For example, LAB B3 is in row B, column 3.
Figure 12. Interconnect Resources
See Figure 15 for details. I/O Element (IOE)
IOE IOE IOE IOE IOE IOE
IOE
IOE
IOE
IOE
Row Interconnect
LAB A1
LAB A2
LAB A3
See Figure 14 for details.
Column Interconnect
IOE
to LAB A5 to LAB A4
IOE
IOE
IOE
LAB B1
LAB B2
LAB B3
Cascade & Carry Chains
to LAB B5 to LAB B4
IOE
IOE
IOE
IOE
IOE
IOE
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FLEX 10K Embedded Programmable Logic Family Data Sheet
I/O Element
An I/O element (IOE) contains a bidirectional I/O buffer and a register that can be used either as an input register for external data that requires a fast setup time, or as an output register for data that requires fast clockto-output performance. In some cases, using an LE register for an input register will result in a faster setup time than using an IOE register. IOEs can be used as input, output, or bidirectional pins. The MAX+PLUS II Compiler uses the programmable inversion option to invert signals from the row and column interconnect automatically where appropriate. Figure 13 shows the IOE block diagram.
Figure 13. I/O Element
2 Dedicated Clock Inputs Peripheral Control Bus
VCC OE[7..0]
Chip-Wide Output Enable
from One Row or Column Channel to Row or Column Interconnect
2
12 VCC
from Row or Column Interconnect
CLK[1..0] CLK[3..2] VCC ENA[5..0]
D
Q
Open-Drain Output
ENA CLRN
Slew-Rate Control
from One Row or Column Channel
VCC CLRn[1..0]
Chip-Wide Reset
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FLEX 10K Embedded Programmable Logic Family Data Sheet
Each IOE selects the clock, clear, clock enable, and output enable controls from a network of I/O control signals called the peripheral control bus. The peripheral control bus uses high-speed drivers to minimize signal skew across devices; it provides up to 12 peripheral control signals that can be allocated as follows:
s s s s
Up to eight output enable signals Up to six clock enable signals Up to two clock signals Up to two clear signals
If more than six clock enable or eight output enable signals are required, each IOE on the device can be controlled by clock enable and output enable signals driven by specific LEs. In addition to the two clock signals available on the peripheral control bus, each IOE can use one of two dedicated clock pins. Each peripheral control signal can be driven by any of the dedicated input pins or the first LE of each LAB in a particular row. In addition, an LE in a different row can drive a column interconnect, which causes a row interconnect to drive the peripheral control signal. The chip-wide reset signal will reset all IOE registers, overriding any other control signals. Tables 7 and 8 list the sources for each peripheral control signal, and the tables show how the output enable, clock enable, clock, and clear signals share 12 peripheral control signals, and shows the rows that can drive global signals.
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FLEX 10K Embedded Programmable Logic Family Data Sheet
Table 7. Peripheral Bus Sources
Peripheral Control Signal
OE0 OE1 OE2 OE3 OE4 OE5 CLKENA0/CLK0/GLOBAL0 CLKENA1/OE6/GLOBAL1 CLKENA2/CLR0 CLKENA3/OE7/GLOBAL2 CLKENA4/CLR1 CLKENA5/CLK1/GLOBAL3
EPF10K10 EPF10K10A
Row A Row A Row B Row B Row C Row C Row A Row A Row B Row B Row C Row C
EPF10K20
EPF10K30 EPF10K30A EPF10K30B
Row A Row B Row C Row D Row E Row F Row A Row B Row C Row D Row E Row F
EPF10K40
EPF10K50 EPF10K50 EPF10K50B
Row A Row B Row D Row F Row H Row J Row A Row C Row E Row G Row I Row J
Row A Row B Row C Row D Row E Row F Row A Row B Row C Row D Row E Row F
Row A Row C Row D Row E Row F Row G Row B Row C Row D Row E Row F Row H
Table 8. More Peripheral Bus Sources
Peripheral Control Signal
OE0 OE1 OE2 OE3 OE4 OE5 CLKENA0/CLK0/GLOBAL0 CLKENA1/OE6/GLOBAL1 CLKENA2/CLR0 CLKENA3/OE7/GLOBAL2 CLKENA4/CLR1 CLKENA5/CLK1/GLOBAL3
EPF10K70
EPF10K100 EPF10K100A EPF10K100B
Row A Row C Row E Row L Row I Row K Row F Row D Row B Row H Row J Row G
EPF10K130V EPF10K130B
Row C Row E Row G Row N Row K Row M Row H Row F Row D Row J Row L Row I
EPF10K250A EPF10K250B
Row E Row G Row I Row P Row M Row O Row J Row H Row F Row L Row N Row K
Row A Row B Row D Row I Row G Row H Row E Row C Row B Row F Row H Row E
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FLEX 10K Embedded Programmable Logic Family Data Sheet
Signals on the peripheral control bus can also drive the four global signals, referred to as GLOBAL0 through GLOBAL3 in Tables 7 and 8. The internally generated signal can drive the global signal, providing the same low-skew, low-delay characteristics for an internally generated signal as for a signal driven by an input. This feature is ideal for internally generated clear or clock signals with high fan-out. The chip-wide output enable pin is an active-low pin that can be used to tri-state all pins on the device. This option can be set in the design file. Additionally, the registers in the IOE can be reset by the chip-wide reset pin.
Row-to-IOE Connections
When an IOE is used as an input signal, it can drive two separate row channels. The signal is accessible by all LEs within that row. When an IOE is used as an output, the signal is driven by a multiplexer that selects a signal from the row channels. Up to eight IOEs connect to each side of each row channel. See Figure 14.
Figure 14. FLEX 10K Row-to-IOE Connections
The values for m and n are provided in Table 9.
IOE1
m
Row FastTrack Interconnect
n
n n
IOE8
m
Each IOE is driven by an m-to-1 multiplexer. Each IOE can drive up to two row channels.
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FLEX 10K Embedded Programmable Logic Family Data Sheet
Table 9 lists the FLEX 10K row-to-IOE interconnect resources.
Table 9. FLEX 10K Row-to-IOE Interconnect Resources
Device
EPF10K10 EPF10K10A EPF10K20 EPF10K30 EPF10K30A EPF10K40 EPF10K50 EPF10K50V EPF10K70 EPF10K100 EPF10K100A EPF10K130V EPF10K250A
Channels per Row (n)
144 144 216 216 216 312 312 312 456
Row Channels per Pin (m)
18 18 27 27 27 39 39 39 57
Column-to-IOE Connections
When an IOE is used as an input, it can drive up to two separate column channels. When an IOE is used as an output, the signal is driven by a multiplexer that selects a signal from the column channels. Two IOEs connect to each side of the column channels. Each IOE can be driven by column channels via a multiplexer. The set of column channels that each IOE can access is different for each IOE. See Figure 15.
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FLEX 10K Embedded Programmable Logic Family Data Sheet
Figure 15. FLEX 10K Column-to-IOE Connections
The values for m and n are provided in Table 10.
Each IOE is driven by a 16-to-1 multiplexer.
m
IOE1
Column Interconnect
n
n
n m
IOE1
Each IOE can drive up to two column channels.
Table 10 lists the FLEX 10K column-to-IOE interconnect resources.
Table 10. FLEX 10K Column-to-IOE Interconnect Resources
Device
EPF10K10 EPF10K10A EPF10K20 EPF10K30 EPF10K30A EPF10K40 EPF10K50 EPF10K50V EPF10K70 EPF10K100 EPF10K100A EPF10K130V EPF10K250A
Channels per Column (n)
24 24 24 24 24 24 24 32 40
Column Channel per Pin (m)
16 16 16 16 16 16 16 24 32
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FLEX 10K Embedded Programmable Logic Family Data Sheet
ClockLock & ClockBoost Features
To support high-speed designs, selected FLEX 10K devices offer optional ClockLock and ClockBoost circuitry containing a phase-locked loop (PLL) that is used to increase design speed and reduce resource usage. The ClockLock circuitry uses a synchronizing PLL that reduces the clock delay and skew within a device. This reduction minimizes clock-to-output and setup times while maintaining zero hold times. The ClockBoost circuitry, which provides a clock multiplier, allows the designer to enhance device area efficiency by resource sharing within the device. ClockBoost allows the designer to distribute a low-speed clock and multiply that clock ondevice. Combined, the ClockLock and ClockBoost features provide significant improvements in system performance and bandwidth. The ClockLock and ClockBoost features in FLEX 10K devices are enabled through the MAX+PLUS II software. External devices are not required to use these features. The output of the ClockLock and ClockBoost circuits is not available at any of the device pins. The ClockLock and ClockBoost circuitry locks onto the rising edge of the incoming clock. The circuit output can only drive the clock inputs of registers; the generated clock cannot be gated or inverted. The dedicated clock pin (GCLK1) supplies the clock to the ClockLock and ClockBoost circuitry. When the dedicated clock pin is driving the ClockLock or ClockBoost circuitry, it cannot drive elsewhere in the device. In designs that require both a multiplied and non-multiplied clock, the clock trace on the board can be connected to GCLK1. With the MAX+PLUS II software, GCLK1 can feed both the ClockLock and ClockBoost circuitry in the FLEX 10K device. However, when both circuits are used, the other clock pin (GCLK0) cannot be used. Figure 16 shows a block diagram of how to enable both the ClockLock and ClockBoost circuits in the MAX+PLUS II software. The example shown is a schematic, but a similar approach applies for designs created in AHDL, VHDL, and Verilog HDL. When the ClockLock and ClockBoost circuits are used simultaneously, the input frequency parameter must be the same for both circuits. In Figure 16, the input frequency must meet the requirements specified when the ClockBoost multiplication factor is two.
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FLEX 10K Embedded Programmable Logic Family Data Sheet
Figure 16. Enabling ClockLock & ClockBoost in the Same Design
CLOCKBOOST=1 INPUT_FREQUENCY=50 CLKLOCK a GCLK1 D Q aout
CLOCKBOOST=2 INPUT_FREQUENCY=50 CLKLOCK b D Q bout
To use both the ClockLock and ClockBoost circuits in the same design, designers must use Revision C EPF10K100GC503-3DX devices and the MAX+PLUS II software, version 7.2 or higher. The revision is identified by the first digit of the date code stamped on top of the device (e.g., date code C9715 identifies a Revision C device).
f Output Configuration
For more information on using the ClockLock and ClockBoost features, see the Clock Management with ClockLock and ClockBoost Features White Paper, which is available from Altera Literature Services. This section discusses PCI clamping diodes, slew-rate control, open-drain output option, and MultiVolt I/O interface for the FLEX 10K devices.
PCI Clamping Diodes
FLEX 10KE (including EPF10K100B) devices have a pull-up clamping diode on every I/O, dedicated input, and dedicated clock pin. PCI clamping diodes clamp the signal to the VCCIO value and are required for 3.3-V PCI compliance. Clamping diodes can also be used to limit overshoot in other systems. Clamping diodes are controlled on a pin-by-pin basis via a logic option in the MAX+PLUS II software. When VCCIO is 3.3 V, a pin which has the clamping diode turned on can be driven by a 2.5-V or 3.3-V signal, but not a 5.0-V signal. When VCCIO is 2.5 V, a pin which has the clamping diode turned on can be driven by a 2.5-V signal, but not a 3.3-V or 5.0-V signal. However, a clamping diode can be turned on for a subset of pins, which would allow a device to bridge between a 3.3-V PCI bus and a 5.0-V device.
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FLEX 10K Embedded Programmable Logic Family Data Sheet
Slew-Rate Control
The output buffer in each IOE has an adjustable output slew rate that can be configured for low-noise or high-speed performance. A slower slew rate reduces system noise and adds a maximum delay of approximately 2.9 ns. The fast slew rate should be used for speed-critical outputs in systems that are adequately protected against noise. Designers can specify the slew rate on a pin-by-pin basis during design entry or assign a default slew rate to all pins on a device-wide basis. The slow slew rate setting affects only the falling edge of the output. Each pin can also be specified as open-drain on a pin-by-pin basis. Additionally, the MAX+PLUS II software can automatically convert tri-state buffers with grounded data inputs to open-drain pins.
Open-Drain Output Option
FLEX 10K devices provide an optional open-drain (electrically equivalent to open-collector) output for each I/O pin. This open-drain output enables the device to provide system-level control signals (e.g., interrupt and write enable signals) that can be asserted by any of several devices. It can also provide an additional wired-OR plane. Open-drain output pins on FLEX10K devices (with a pull-up resistor to the 5.0-V supply) can drive 5.0-V CMOS input pins that require a VIH of 3.5 V. When the open-drain pin is active, it will drive low. When the pin is inactive, the trace will be pulled up to 5.0 V by the resistor. The opendrain pin will only drive low or tri-state, never high. Therefore, a connection will not exist between the 3.3-V and 5.0-V power supplies. The rise time is dependent on the value of the pull-up resistor and load impedance. The IOL current specification should be considered when selecting a pull-up resistor.
MultiVolt I/O Interface
The FLEX 10K device architecture supports the MultiVolt I/O interface feature, which allows FLEX 10K, and FLEX 10KA, and FLEX 10KE devices to interface with systems of differing supply voltages. These devices have one set of VCC pins for internal operation and input buffers (VCCINT), and another set for I/O output drivers (VCCIO). Table 11 describes the FLEX 10K device supply voltages and MultiVolt I/O support levels.
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FLEX 10K Embedded Programmable Logic Family Data Sheet
Table 11. Supply Voltages & MultiVolt I/O Support Levels
Device Family Supply Voltage (V) VCCINT
FLEX 10K EPF10K50V EPF10K130V FLEX 10KA FLEX 10KE (including the EPF10K100B device) 5.0 5.0 3.3 3.3 3.3 3.3 2.5 2.5
MultiVolt I/O Support Levels (V) Input
3.3 or 5.0 3.3 or 5.0 3.3 or 5.0 3.3 or 5.0 2.5, 3.3, or 5.0 2.5, 3.3, or 5.0 2.5, 3.3, or 5.0 2.5, 3.3, or 5.0
VCCIO
5.0 3.3 3.3 3.3 3.3 2.5 3.3 2.5
Output
5.0 3.3 or 5.0 3.3 or 5.0 3.3 or 5.0 3.3 or 5.0 2.5 3.3 or 5.0 2.5
IEEE 1149.1 (JTAG) Boundary-Scan Support
All FLEX 10K devices provide JTAG BST circuitry that comply with the IEEE Std. 1149.1-1990 specification. All FLEX 10K devices can also be configured using the JTAG pins through the BitBlaster serial download cable, ByteBlaster parallel port download cable, ByteBlasterMV parallel port download cable, or via hardware that uses the Jam programming and test language. JTAG BST can be performed before or after configuration, but not during configuration. FLEX 10K devices support the JTAG instructions shown in Table 12.
Table 12. FLEX 10K JTAG Instructions
JTAG Instruction
SAMPLE/PRELOAD EXTEST BYPASS
Description
Allows a snapshot of signals at the device pins to be captured and examined during normal device operation, and permits an initial data pattern output at the device pins. Allows the external circuitry and board-level interconnections to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through a selected device to adjacent devices during normal device operation. Selects the user electronic signature (UESCODE) register and places it between the TDI and TDO pins, allowing the UESCODE to be serially shifted out of TDO. Selects the IDCODE register and places it between TDI and TDO, allowing the IDCODE to be serially shifted out of TDO. These instructions are used when configuring a FLEX 10K device via JTAG ports with a BitBlaster, ByteBlaster, or ByteBlasterMV download cable, or using a Jam File (.jam) via an embedded processor.
UESCODE IDCODE ICR Instructions
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FLEX 10K Embedded Programmable Logic Family Data Sheet
f
For more information on JTAG operation, see Application Note 39 (JTAG Boundary-Scan Testing in Altera Devices). For more information on the BitBlaster, ByteBlaster, or ByteBlasterMV download cables, go to the BitBlaster Serial Download Cable Data Sheet, ByteBlaster Parallel Port Download Cable Data Sheet, and ByteBlasterMV Parallel Port Download Cable Data Sheet in this data book. For information on the Jam language, refer to the Jam Programming and Test Language Specification. Figure 17 shows the timing requirements for the JTAG signals.
Figure 17. JTAG Waveforms
TMS
TDI
tJCP tJCH tJCL tJPSU tJPH
TCK
tJPZX tJPCO tJPXZ
TDO
tJSSU tJSH
Signal to Be Captured Signal to Be Driven
tJSZX
tJSCO
tJSXZ
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FLEX 10K Embedded Programmable Logic Family Data Sheet
Table 13 shows the timing parameters and values for FLEX 10K devices.
Table 13. JTAG Timing Parameters & Values
Symbol
tJCP tJCH tJCL tJPSU tJPH tJPCO tJPZX tJPXZ tJSSU tJSH tJSCO tJSZX tJSXZ TCK clock period TCK clock high time TCK clock low time JTAG port setup time JTAG port hold time JTAG port clock to output JTAG port high impedance to valid output JTAG port valid output to high impedance Capture register setup time Capture register hold time Update register clock to output Update register high-impedance to valid output Update register valid output to high impedance 20 45 35 35 35
Parameter
Min
100 50 50 20 45
Max
Unit
ns ns ns ns ns
25 25 25
ns ns ns ns ns ns ns ns
Generic Testing
Each FLEX 10K device is functionally tested. Complete testing of each configurable SRAM bit and all logic functionality ensures 100% yield. AC test measurements for FLEX 10K devices are made under conditions equivalent to those shown in Figure 18. Multiple test patterns can be used to configure devices during all stages of the production flow.
Figure 18. FLEX 10K AC Test Conditions
Power supply transients can affect AC measurements. Simultaneous transitions of multiple outputs should be avoided for accurate measurement. Threshold tests must not be performed under AC conditions. Large-amplitude, fast-ground-current transients normally occur as the device outputs discharge the load capacitances. When these transients flow through the parasitic inductance between the device ground pin and the test system ground, significant reductions in observable noise immunity can result. Numbers in parentheses are for 3.3-V devices or outputs. Numbers in brackets are for 2.5-V devices or outputs.
VCC 464 (703 ) [521 ] Device Output 250 (8.06 k) [481 ] Device input rise and fall times < 3 ns to Test System
C1 (includes JIG capacitance)
Altera Corporation
39
FLEX 10K Embedded Programmable Logic Family Data Sheet
Operating Conditions
Symbol
V CC VI I OUT T STG T AMB TJ
The following tables provide information on absolute maximum ratings, recommended operating conditions, DC operating conditions, and capacitance for 5.0-V and 3.3-V FLEX 10K devices.
FLEX 10K 5.0-V Device Absolute Maximum Ratings
Parameter
Supply voltage DC input voltage DC output current, per pin Storage temperature Ambient temperature Junction temperature No bias Under bias
Note (1)
Conditions Min
-2.0 -2.0 -25 -65 -65
Max
7.0 7.0 25 150 135 150 135
Unit
V V mA C C C C
With respect to ground
Note (2)
Ceramic packages, under bias PQFP, TQFP, RQFP, and BGA packages, under bias
FLEX 10K 5.0-V Device Recommended Operating Conditions
Symbol
V CCINT V CCIO
Parameter
Supply voltage for internal logic and Notes (3), (4) input buffers Supply voltage for output buffers, 5.0-V operation Supply voltage for output buffers, 3.3-V operation
Conditions
Min
Max
Unit
V V V V V C C C C ns ns
4.75 (4.50) 5.25 (5.50) 4.75 (4.50) 5.25 (5.50) 3.00 (3.00) 3.60 (3.60) 0 0 V CCINT V CCIO 70 85 85 100 40 40
Notes (3), (4) Notes (3), (4)
VI VO TA TJ tR tF
Input voltage Output voltage Ambient temperature Operating temperature Input rise time Input fall time For commercial use For industrial use For commercial use For industrial use
0 -40 0 -40
40
Altera Corporation
FLEX 10K Embedded Programmable Logic Family Data Sheet
FLEX 10K 5.0-V Device DC Operating Conditions
Symbol
V IH V IL V OH
Notes (5), (6)
Min
2.0 -0.3
Parameter
High-level input voltage Low-level input voltage 5.0-V high-level TTL output voltage 3.3-V high-level TTL output voltage 3.3-V high-level CMOS output voltage
Conditions
Typ
Max
V CCINT + 0.3 0.8
Unit
V V V V V
I OH = -4 mA DC, V CCIO = 4.75 V, Note (7) I OH = -4 mA DC, V CCIO = 3.00 V, Note (7)
2.4 2.4
I OH = -0.1 mA DC, V CCIO = 3.00 V, Note (7) V CCIO - 0.2 I OL = 12 mA DC, V CCIO = 4.75 V, Note (8) I OL = 12 mA DC, V CCIO = 3.00 V, Note (8) I OL = 0.1 mA DC, V CCIO = 3.00 V, Note (8) V I = V CC or ground V O = V CC or ground V I = ground, no load -10 -40 0.5 0.45 0.45 0.2 10 40 10
V OL
5.0-V low-level TTL output voltage 3.3-V low-level TTL output voltage 3.3-V low-level CMOS output voltage
V V V A A mA
II I OZ I CC0
Input pin leakage current Tri-stated I/O pin leakage current V CC supply current (standby)
5.0-V Device Capacitance of EPF10K10, EPF10K20 & EPF10K30 Devices
Symbol Parameter Conditions
Note (9)
84-Pin 144-Pin 208-Pin 208-Pin 240-Pin 356-Pin Unit PLCC TQFP PQFP RQFP RQFP BGA EPF10K10 EPF10K10 EPF10K10 EPF10K20 EPF10K20 EPF10K30 EPF10K20 EPF10K30 EPF10K30 Min Max Min Max Min Max Min Max Min Max Min Max
CIN CINCLK
Input capacitance Input capacitance on dedicated clock pin Output capacitance
VIN = 0 V, f = 1.0 MHz VIN = 0 V, f = 1.0 MHz
8 12
8 12
8 12
8 12
8 12
8 12
pF pF
COUT
VOUT = 0 V, f = 1.0 MHz
8
8
8
8
8
8
pF
Altera Corporation
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FLEX 10K Embedded Programmable Logic Family Data Sheet
5.0-V Device Capacitance of EPF10K40, EPF10K50, EPF10K70 & EPF10K100 Devices
Symbol Parameter Conditions 208-Pin RQFP EPF10K40 Min
CIN CINCLK Input capacitance Input capacitance on dedicated clock pin Output capacitance VIN = 0 V, f = 1.0 MHz VIN = 0 V, f = 1.0 MHz
Note (9)
240-Pin RQFP 356-Pin BGA 403-Pin PGA 503-Pin PGA Unit EPF10K40 EPF10K50 EPF10K50 EPF10K70 EPF10K50 EPF10K100 EPF10K70 Min Max
10 15
Max
10 15
Min
Max
10 15
Min
Max
10 15
Min
Max
10 15 pF pF
COUT
VOUT = 0 V, f = 1.0 MHz
10
10
10
10
10
pF
Notes to tables:
(1) (2) (3) (4) (5) (6) (7) (8) (9) See Operating Requirements for Altera Devices Data Sheet in this data book. Minimum DC input is 0.3 V. During transitions, the inputs may undershoot to 2.0 V or overshoot to 7.0 V for periods shorter than 20 ns under no-load conditions. Numbers in parentheses are for industrial-temperature-range devices. Maximum VCC rise time is 100 ms. VCC must rise monotonically. Typical values are for T A = 25 C and V CC = 5.0 V. These values are specified under OFLEX 10K 5.0-V Device Recommended Operating ConditionsO on page 40. The IOH parameter refers to high-level TTL or CMOS output current. The IOL parameter refers to low-level TTL or CMOS output current. This parameter applies to open-drain pins as well as output pins. Capacitance is sample-tested only.
Figure 19 shows the typical output drive characteristics of FLEX 10K devices with 5.0-V and 3.3-V VCCIO. The output driver is compatible with the PCI Local Bus Specification, Revision 2.1 (with 5.0-V VCCIO.)
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Altera Corporation
FLEX 10K Embedded Programmable Logic Family Data Sheet
Figure 19. Output Drive Characteristics of FLEX 10K Devices
5.0-V
150
3.3-V IOL Output Current (mA) Typ.
150
IOL
Output Current (mA) Typ.
120
120
90
VCCINT = 5.0 V VCCIO = 5.0 V Room Temperature
90
VCCINT = 5.0 V VCCIO = 3.3 V Room Temperature
60
60 45 30
IOH
30
IOH
IO
IO
1
2
3
4
5
1
2
3 3.3
4
5
VO Output Voltage (V)
VO Output Voltage (V)
EPF10K50V & EPF10K130V Device Absolute Maximum Ratings
Symbol
V CC VI I OUT T STG T AMB TJ
Note (1)
Min
-0.5 -2.0 -25 -65 -65
Parameter
Supply voltage DC input voltage DC output current, per pin Storage temperature Ambient temperature Junction temperature No bias Under bias
Conditions
With respect to ground
Max
4.6 5.7 25 150 135 150 135
Unit
V V mA C C C C
Note (2)
Ceramic packages, under bias RQFP and BGA packages, under bias
EPF10K50V & EPF10K130V Device Recommended Operating Conditions
Symbol
V CCINT V CCIO VI VO TA TJ tR tF
Parameter
Supply voltage for internal logic and Notes (3), (4) input buffers Supply voltage for output buffers Input voltage Output voltage Ambient temperature Operating temperature Input rise time Input fall time
Conditions
Min
Max
Unit
V V V V C C C C ns ns
3.00 (3.00) 3.60 (3.60) 3.00 (3.00) 3.60 (3.60) 0 0 0 -40 0 -40 5.3 V CCIO 70 85 85 100 40 40
Notes (3), (4) Note (5)
For commercial use For industrial use For commercial use For industrial use
Altera Corporation
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FLEX 10K Embedded Programmable Logic Family Data Sheet
EPF10K50V & EPF10K130V Device DC Operating Conditions
Symbol
V IH V IL V OH
Notes (6), (7)
Min
2.0 -0.3
Parameter
High-level input voltage Low-level input voltage 3.3-V high-level TTL output voltage 3.3-V high-level CMOS output voltage
Conditions
Typ
Max
5.3 0.8
Unit
V V V V
I OH = -4 mA DC, Note (8) I OH = -0.1 mA DC, Note (8) I OL = 4 mA DC, Note (9) I OL = 0.1 mA DC, Note (9) V I = V CC or ground V O = V CC or ground V I = ground, no load
2.4 V CCIO- 0.2 0.45 0.2 -10 -10 0.3 10 10 10
V OL
3.3-V low-level TTL output voltage 3.3-V low-level CMOS output voltage
V V A A mA mA
II I OZ I CC0
Input pin leakage current Tri-stated I/O pin leakage current V CC supply current (standby)
Note (10)
EPF10K50V & EPF10K130V Device Capacitance
Symbol Parameter Conditions
Note (11)
240-Pin 356-Pin BGA 599-Pin PGA 600-Pin PGA Unit EPF10K50V EPF10K50V EPF10K130V EPF10K130V Min Max
10 15 10
Min
Max
10 15 10
Min
Max
10 15 10
Min
Max
10 15 10 pF pF pF
CIN CINCLK COUT
Input capacitance Input capacitance on dedicated clock pin Output capacitance
VIN = 0 V, f = 1.0 MHz VIN = 0 V, f = 1.0 MHz VOUT = 0 V, f = 1.0 MHz
Notes to tables:
See Operating Requirements for Altera Devices Data Sheet in this data book. Minimum DC input is 0.3 V. During transitions, the inputs may undershoot to -2.0 V or overshoot to 5.7 V for periods shorter than 20 ns under no-load conditions. (3) Numbers in parentheses are for industrial-temperature-range devices. (4) Maximum VCC rise time is 100 ms. VCC must rise monotonically. (5) Inputs of EPF10K50V and EPF10K130V devices may be driven before VCCINT is powered. (6) Typical values are for T A = 25 C and V CC = 3.3 V. (7) These values are specified under OFLEX 10K 3.3-V Device Recommended Operating ConditionsO on page 45. (8) The IOH parameter refers to high-level TTL or CMOS output current. (9) The IOL parameter refers to low-level TTL or CMOS output current. This parameter applies to open-drain pins as well as output pins. (10) This parameter applies to -1 speed grade EPF10K50V devices. (11) Capacitance is sample-tested only. (1) (2)
Figure 20 shows the typical output drive characteristics of EPF10K50V and EPF10K130V devices.
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Altera Corporation
FLEX 10K Embedded Programmable Logic Family Data Sheet
Figure 20. Output Drive Characteristics of EPF10K50V & EPF10K130V Devices
Output Current (mA) Typ.
60
40
IOL
Vcc = 3.3 V Room Temperature IOH
20
IO
1
2
3
VO Output Voltage (V)
FLEX 10KA 3.3-V Device Absolute Maximum Ratings
Symbol
V CC VI I OUT T STG T AMB TJ
Note (1)
Conditions Min
-0.5 -2.0 -25 -65 -65
Parameter
Supply voltage DC input voltage DC output current, per pin Storage temperature Ambient temperature Junction temperature No bias Under bias
Max
4.6 5.7 25 150 135 150 135
Unit
V V mA C C C C
With respect to ground, Note (2)
Ceramic packages, under bias PQFP, TQFP, RQFP, and BGA packages, under bias
FLEX 10KA 3.3-V Device Recommended Operating Conditions
Symbol
V CCINT V CCIO
Parameter
Supply voltage for internal logic and input buffers Supply voltage for output buffers, 3.3-V operation Supply voltage for output buffers, 2.5-V operation
Conditions
Notes (3), (4) Notes (3), (4) Notes (3), (4) Note (5)
For commercial use For industrial use For commercial use For industrial use
Min
Max
Unit
V V V V V C C C C ns ns
3.00 (3.00) 3.60 (3.60) 3.00 (3.00) 3.60 (3.60) 2.30 (2.30) 2.70 (2.70) 0 0 0 -40 0 -40 5.3 V CCIO 70 85 85 100 40 40
VI VO TA TJ tR tF
Input voltage Output voltage Ambient temperature Operating temperature Input rise time Input fall time
Altera Corporation
45
FLEX 10K Embedded Programmable Logic Family Data Sheet
FLEX 10KA 3.3-V Device DC Operating Conditions
Symbol
V IH V IL V OH
Notes (6), (7)
Min
1.7 or 0.5 x V CCINT, whichever is lower -0.5
Parameter
High-level input voltage Low-level input voltage 3.3-V high-level TTL output voltage 3.3-V high-level CMOS output voltage
Conditions
Typ
Max
5.3 0.3 x VCCINT
Unit
V V V V V
I OH = -4 mA DC, V CCIO = 3.00 V, Note (8) I OH = -0.1 mA DC, V CCIO = 3.00 V, Note (8)
2.4 V CCIO - 0.2 0.9 x VCCIO
3.3-V high-level PCI output voltage I OH = -0.5 mA DC, V CCIO = 3.00 to 3.60 V, Note (8) 2.5-V high-level output voltage I OH = -0.1 mA DC, V CCIO = 2.30 V, Note (8) I OH = -1 mA DC, V CCIO = 2.30 V, Note (8) I OH = -2 mA DC, V CCIO = 2.30 V, Note (8) V OL 3.3-V low-level TTL output voltage I OL = 4 mA DC, V CCIO = 3.00 V, Note (9) 3.3-V low-level CMOS output voltage I OL = 0.1 mA DC, V CCIO = 3.00 V, Note (9)
2.1 2.0 1.7 0.45 0.2 0.1 x VCCIO
V V V V V V
3.3-V low-level PCI output voltage I OL = 1.5 mA DC, V CCIO = 3.00 to 3.60 V, Note (9) 2.5-V low-level output voltage I OL = 0.1 mA DC, V CCIO = 2.30 V, Note (9) I OL = 1 mA DC, V CCIO = 2.30 V, Note (9) I OL = 2 mA DC, V CCIO = 2.30 V, Note (9) II I OZ I CC0 Input pin leakage current Tri-stated I/O pin leakage current V CC supply current (standby) V I = V CC or ground V O = V CC or ground V I = ground, no load -10 -10 0.3 10
0.2 0.4 0.7 10 10
V V V A A mA mA
Note (10)
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Altera Corporation
FLEX 10K Embedded Programmable Logic Family Data Sheet
3.3-V Device Capacitance of EPF10K10A & EPF10K30A Devices
Symbol Parameter Conditions
Note (11), (12)
240-Pin 356-Pin Unit 208-Pin 144-Pin RQFP BGA RQFP TQFP EPF10K10A EPF10K10A EPF10K30A EPF10K30A EPF10K30A EPF10K30A Min Max
8 12 8
Min
Max
8 12 8
Min
Max
8 12 8
Min
Max
8 12 8 pF pF pF
CIN CINCLK COUT
Input capacitance
VIN = 0 V, f = 1.0 MHz
Input capacitance on dedicated VIN = 0 V, clock pin f = 1.0 MHz Output capacitance VOUT = 0 V, f = 1.0 MHz
3.3-V Device Capacitance of EPF10K100A Devices
Symbol Parameter
Note (11), (12)
240-Pin RQFP EPF10K100A Min Max
10 15 10
Conditions
356-Pin BGA EPF10K100A Min Max
10 15 10
Unit
CIN CINCLK COUT
Input capacitance Output capacitance
VIN = 0 V, f = 1.0 MHz VOUT = 0 V, f = 1.0 MHz
pF pF pF
Input capacitance on dedicated clock pin VIN = 0 V, f = 1.0 MHz
3.3-V Device Capacitance of EPF10K250A Devices
Symbol Parameter
Note (11), (12)
599-Pin PGA EPF10K250A Min Max
10 15 10
Conditions
600-Pin BGA EPF10K250A Min Max
10 15 10
Unit
CIN CINCLK COUT
Input capacitance Output capacitance
VIN = 0 V, f = 1.0 MHz VOUT = 0 V, f = 1.0 MHz
pF pF pF
Input capacitance on dedicated clock pin VIN = 0 V, f = 1.0 MHz
Altera Corporation
47
FLEX 10K Embedded Programmable Logic Family Data Sheet Notes to tables:
See Operating Requirements for Altera Devices Data Sheet in this data book. Minimum DC input is 0.3 V. During transitions, the inputs may undershoot to 2.0 V or overshoot to 5.7 V for periods shorter than 20 ns under no-load conditions. (3) Numbers in parentheses are for industrial-temperature-range devices. (4) Maximum VCC rise time is 100 ms, and VCC must rise monotonically. (5) Inputs of FLEX 10KA devices may be driven before VCCINT and VCCIO are powered. (6) Typical values are for T A = 25 C and V CC = 3.3 V. (7) These values are specified under OFLEX 10K 3.3-V Device Recommended Operating ConditionsO on page 45. (8) The IOH parameter refers to high-level TTL, PCI, or CMOS output current. (9) The IOL parameter refers to low-level TTL, PCI, or CMOS output current. This parameter applies to open-drain pins as well as output pins. (10) This parameter applies to EPF10K100A devices. (11) Capacitance is sample-tested only. (12) The information in this table is preliminary. For the most up-to-date information, contact Altera Applications. (1) (2)
Figure 21 shows the typical output drive characteristics of FLEX 10K devices with 3.3-V and 2.5-V V CCIO. The output driver is compatible with the 3.3-V PCI Local Bus Specification, Revision 2.1 (with 3.3-V V CCIO.)
Figure 21. Output Drive Characteristics for FLEX 10KA Devices
3.3-V
60
2.5-V
60
IOL
50 50
IOL
Output Current (mA) Typ.
40
Output Current (mA) Typ.
30
VCCINT = 3.3 V VCCIO = 3.3 V Room Temperature
40
30
VCCINT = 3.3 V VCCIO = 2.5 V Room Temperature
20
20
IO
IO
10
IOH
10
IOH
1
2
3
4
1
2
3
4
VO Output Voltage (V)
VO Output Voltage (V)
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Altera Corporation
FLEX 10K Embedded Programmable Logic Family Data Sheet
Timing Model
The continuous, high-performance FastTrack Interconnect routing resources ensure predictable performance and accurate simulation and timing analysis. This predictable performance contrasts with that of FPGAs, which use a segmented connection scheme and therefore have unpredictable performance. Device performance can be estimated by following the signal path from a source, through the interconnect, to the destination. For example, the registered performance between two LEs on the same row can be calculated by adding the following parameters:
s s s s
LE register clock-to-output delay (tCO) Interconnect delay (tSAMEROW) LE look-up table delay (tLUT) LE register setup time (tSU)
The routing delay depends on the placement of the source and destination LEs. A more complex registered path may involve multiple combinatorial LEs between the source and destination LEs. Timing simulation and delay prediction are available with the MAX+PLUS II Simulator and Timing Analyzer, or with industrystandard EDA tools. The Simulator offers both pre-synthesis functional simulation to evaluate logic design accuracy and post-synthesis timing simulation with 0.1-ns resolution. The Timing Analyzer provides pointto-point timing delay information, setup and hold time analysis, and device-wide performance analysis. Figure 22 shows the overall timing model, which maps the possible paths to and from the various elements of the FLEX 10K device.
Figure 22. FLEX 10K Device Timing Model
Dedicated Clock/Input Interconnect I/O Element
Logic Element
Embedded Array Block
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49
FLEX 10K Embedded Programmable Logic Family Data Sheet
Figures 23 through 25 show the delays that correspond to various paths and functions within the LE, IOE, and EAB timing models.
Figure 23. FLEX 10K Device LE Timing Model
Carry-In Cascade-In
LUT Delay Data-In
Register Delays
tLUT tRLUT tCLUT
Packed Register Delay
tPACKED
Register Control Delay Control-In
tCO tCOMB tSU tH tPRE tCLR
Data-Out
tC tEN
Carry Chain Delay tCGENR
tCGEN tCICO tLABCARRY
tCASC
tLABCASC
Carry-Out
Cascade-Out
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Altera Corporation
FLEX 10K Embedded Programmable Logic Family Data Sheet
Figure 24. FLEX 10K Device IOE Timing Model
Output Data Delay Data-In I/O Register Delays Output Delays
tIOD
I/O Element Contol Delay Clock Enable Clear Clock Output Enable
tIOCO tIOCOMB tIOSU tIOH tIOCLR
tIOC tINREG
Input Register Delay I/O Register Feedback Delay
tOD1 tOD2 tOD3 tXZ tZX1 tZX2 tZX3
Data Feedback into FastTrack Interconnect
tIOFD
Input Delay
tINCOMB
Figure 25. FLEX 10K Device EAB Timing Model
EAB Data Input Delays Data-In Address Input Register Delays RAM/ROM Block Delays Output Register Delays EAB Output Delay
tEABDATA1 tEABDATA2
Write Enable Input Delays
WE
tEABWE1 tEABWE2
EAB Clock Delay
tEABCO tEABBYPASS tEABSU tEABH tEABCH tEABCL
tAA tDD tWP tWDSU tWDH tWASU tWAH tWO
tEABCO tEABBYPASS tEABSU tEABH tEABCH tEABCL
tEABOUT
Data-Out
Input Register Clock Output Register Clock
tEABCLK
Tables 14 through 18 describe the FLEX 10K device internal timing parameters. These internal timing parameters are expressed as worst-case values. Using hand calculations, these parameters can be used to estimate design performance. However, before committing designs to silicon, actual worst-case performance should be modeled using timing simulation and analysis. Tables 19 and 20 describe FLEX 10K external timing parameters.
Altera Corporation
51
FLEX 10K Embedded Programmable Logic Family Data Sheet
Table 14. LE Timing Microparameters
Symbol
tLUT tCLUT tRLUT tPACKED tEN tCICO tCGEN tCGENR tCASC tC tCO tCOMB tSU tH tPRE tCLR tCH tCL
LUT delay for data-in LUT delay for carry-in
Note (1)
Parameter Conditions
LUT delay for LE register feedback Data-in to packed register delay LE register enable delay Carry-in to carry-out delay Data-in to carry-out delay LE register feedback to carry-out delay Cascade-in to cascade-out delay LE register control signal delay LE register clock-to-output delay Combinatorial delay LE register setup time before clock; LE register recovery time after asynchronous clear, preset, or load LE register hold time after clock LE register preset delay LE register clear delay Minimum clock high time from clock pin Minimum clock low time from clock pin
Table 15. IOE Timing Microparameters (Part 1 of 2)
Symbol
tIOD tIOC tIOCO tIOCOMB tIOSU tIOH tIOCLR tOD1 tOD2 tOD3
IOE data delay IOE register control signal delay IOE register clock-to-output delay IOE combinatorial delay
Note (1)
Conditions
Parameter
IOE register data setup time before clock; IOE register recovery time after asynchronous clear IOE register data hold time after clock IOE register clear time Output buffer and pad delay, slow slew rate = off, VCCIO = VCCINT Output buffer and pad delay, slow slew rate = off, VCCIO = low voltage Output buffer and pad delay, slow slew rate = on C1 = 35 pF, Note (2) C1 = 35 pF, Note (3) C1 = 35 pF, Note (4)
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Altera Corporation
FLEX 10K Embedded Programmable Logic Family Data Sheet
Table 15. IOE Timing Microparameters (Part 2 of 2)
Symbol
tXZ tZX1 tZX2 tZX3 tINREG tIOFD tINCOMB
IOE output buffer disable delay
Note (1)
Conditions
C1 = 35 pF, Note (2) C1 = 35 pF, Note (3) C1 = 35 pF, Note (4)
Parameter
IOE output buffer enable delay, slow slew rate = off, VCCIO = VCCINT IOE output buffer enable delay, slow slew rate = off, VCCIO = low voltage IOE output buffer enable delay, slow slew rate = on IOE input pad and buffer to IOE register delay IOE register feedback delay IOE input pad and buffer to FastTrack Interconnect delay
Table 16. EAB Timing Microparameters
Symbol
tEABDATA1 tEABDATA2 tEABWE1 tEABWE2 tEABCLK tEABCO tEABBYPASS tEABSU tEABH tEABCH tEABCL tAA tWP tWDSU tWDH tWASU tWAH tWO tDD tEABOUT
Note (1)
Parameter Conditions
Data or address delay to EAB for combinatorial input Data or address delay to EAB for registered input Write enable delay to EAB for combinatorial input Write enable delay to EAB for registered input EAB register clock delay EAB register clock-to-output delay Bypass register delay EAB register setup time before clock EAB register hold time after clock Clock high time Clock low time Address access delay Write pulse width Data setup time before falling edge of write pulse Data hold time after falling edge of write pulse Address setup time before rising edge of write pulse Address hold time after falling edge of write pulse Write enable to data output valid delay Data-in to data-out valid delay Data-out delay
Note (5) Note (5) Note (5) Note (5)
Altera Corporation
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FLEX 10K Embedded Programmable Logic Family Data Sheet
Table 17. EAB Timing Macroparameters
Symbol
tEABAA tEABRCCOMB tEABRCREG tEABWP tEABWCCOMB tEABWCREG tEABDD tEABDATACO tEABDATASU tEABDATAH tEABWESU tEABWESH tEABWDSU tEABWDH tEABWASU tEABWAH tEABWO
EAB address access delay
Notes (1), (6)
Parameter Conditions
EAB asynchronous read cycle time EAB synchronous read cycle time EAB write pulse width EAB asynchronous write cycle time EAB synchronous write cycle time EAB data-in to data-out valid delay EAB clock-to-output delay when using output registers EAB data/address setup time before clock when using input register EAB data/address hold time after clock when using input register EAB WE setup time before clock when using input register EAB WE hold time after clock when using input register EAB data setup time before falling edge of write pulse when not using input registers EAB data hold time after falling edge of write pulse when not using input registers EAB address setup time before rising edge of write pulse when not using input registers EAB address hold time after falling edge of write pulse when not using input registers EAB write enable to data output valid delay
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Altera Corporation
FLEX 10K Embedded Programmable Logic Family Data Sheet
Table 18. Interconnect Timing Microparameters
Symbol
tSAMELAB tSAMEROW tSAMECOLUMN tDIFFROW tTWOROWS tLEPERIPH tLABCARRY tLABCASC tDIN2IOE tDIN2LE tDCLK2IOE tDCLK2LE tDIN2DATA
Note (1)
Conditions
Parameter
Routing delay for an LE driving another LE in the same LAB
Routing delay for a row IOE, LE, or EAB driving a row IOE, LE, or EAB in the Note (7) same row Routing delay for an LE driving an IOE in the same column
Note (7)
Routing delay for a column IOE, LE, or EAB driving an LE or EAB in a different Note (7) row Routing delay for a row IOE or EAB driving an LE or EAB in a different row Routing delay for an LE driving a control signal of an IOE via the peripheral control bus Routing delay for the carry-out signal of an LE driving the carry-in signal of a different LE in a different LAB Routing delay for the cascade-out signal of an LE driving the cascade-in signal of a different LE in a different LAB Delay from dedicated input pin to IOE control input Delay from dedicated input pin to LE or EAB control input Delay from dedicated clock pin to IOE clock Delay from dedicated clock pin to LE or EAB clock Delay from dedicated input or clock to LE or EAB data
Note (7) Note (7)
Note (7) Note (7) Note (7) Note (7) Note (7)
Table 19. External Reference Timing Parameters
Symbol
tDRR
Note (8)
Conditions
Parameter
Register-to-register delay via four LEs, three row interconnects, and four local Note (9) interconnects
Table 20. External Timing Parameters
Symbol
tINSU tINH tOUTCO tODH
Note (10)
Parameter Conditions
Setup time with global clock at IOE register Hold time with global clock at IOE register Clock-to-output delay with global clock at IOE register Output data hold time after clock C1 = 35 pF, Note (11)
Altera Corporation
55
FLEX 10K Embedded Programmable Logic Family Data Sheet Notes to tables:
(1) Microparameters are timing delays contributed by individual architectural elements. These parameters cannot be measured explicitly. (2) Operating conditions: VCCIO = 5.0 V 5% for commercial use in FLEX 10K devices. VCCIO = 5.0 V 10% for industrial use in FLEX 10K devices. VCCIO = 3.3 V 10% for commercial or industrial use in FLEX 10KA devices. (3) Operating conditions: VCCIO = 3.3 V 10% for commercial or industrial use in FLEX 10K devices. VCCIO = 2.5 V 0.2 V for commercial or industrial use in FLEX 10KA devices. (4) Operating conditions: VCCIO = 2.5 V, 3.3 V, or 5.0 V. (5) Because the RAM in the EAB is self-timed, this parameter can be ignored when the WE signal is registered. (6) EAB macroparameters are internal parameters that can simplify predicting the behavior of an EAB at its boundary; these parameters are calculated by summing selected microparameters. (7) These parameters are worst-case values for typical applications. Post-compilation timing simulation and timing analysis are required to determine actual worst-case performance. (8) External reference timing parameters are factory-tested, worst-case values specified by Altera. A representative subset of signal paths is tested to approximate typical device applications. (9) Contact Altera Applications for test circuit specifications and test conditions. (10) These timing parameters are sample-tested only. (11) This parameter is a guideline that is sample-tested only and based on extensive device characterization. This parameter applies for both global and non-global clocking and for LE, EAB, and IOE registers.
Figures 26 and 27 show the asynchronous and synchronous timing waveforms, respectively, for the EAB macroparameters in Table 16.
Figure 26. EAB Asynchronous Timing Waveforms
EAB Asynchronous Read
WE Address a0
tEABAA
a1
a2
tEABRCCOMB
a3
Data-Out
d0
d1
d2
d3
EAB Asynchronous Write
WE
tEABWP tEABWDSU tEABWDH
Data-In
din0
tEABWASU tEABWCCOMB
din1
tEABWAH
Address
a0
a1
tEABDD
a2
Data-Out
din0
din1
dout2
56
Altera Corporation
FLEX 10K Embedded Programmable Logic Family Data Sheet
Figure 27. EAB Synchronous Timing Waveforms
EAB Synchronous Read
WE
Address
a0
tEABDATASU
a1
tEABDATAH
a2
tEABRCREG
a3
CLK
tEABDATACO
Data-Out
d1
d2
EAB Synchronous Write
WE
Data-In
din1
din2
din3
Address
a0
a1
tEABWESU tEABDATASU
a2
tEABDATAH
a3
tEABWEH
a2
CLK
tEABWCREG tEABDATACO
Data-Out
dout0
dout1
din1
din2
din3
din2
Altera Corporation
57
FLEX 10K Embedded Programmable Logic Family Data Sheet
EPF10K10 & EPF10K20 Device Internal & External Timing Parameters EPF10K10 & EPF10K20 Device LE Timing Microparameters
Symbol -3 Speed Grade Min
tLUT tCLUT tRLUT tPACKED tEN tCICO tCGEN tCGENR tCASC tC tCO tCOMB tSU tH tPRE tCLR tCH tCL
Note:
(1) All timing parameters are described in Tables 14 through 20 in this data sheet.
Note (1)
-4 Speed Grade Min Max
1.7 0.7 1.9 0.9 1.2 0.3 1.2 1.2 0.9 1.5 1.1 0.6 2.5 1.6 ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1.2 1.2 4.0 4.0 ns ns ns ns
Unit
Max
1.4 0.6 1.5 0.6 1.0 0.2 0.9 0.9 0.8 1.3 0.9 0.5
1.3 1.4 1.0 1.0 4.0 4.0
58
Altera Corporation
FLEX 10K Embedded Programmable Logic Family Data Sheet
EPF10K10 & EPF10K20 Device IOE Timing Microparameters
Symbol -3 Speed Grade Min
tIOD tIOC tIOCO tIOCOMB tIOSU tIOH tIOCLR tOD1 tOD2 tOD3 tXZ tZX1 tZX2 tZX3 tINREG tIOFD tINCOMB
Note:
(1)
Note (1)
-4 Speed Grade Min Max
1.6 0.7 0.2 0.0 3.2 1.2 ns ns ns ns ns ns 1.2 3.5 6.4 8.2 5.4 5.4 8.3 10.1 7.5 3.5 3.5 ns ns ns ns ns ns ns ns ns ns ns
Unit
Max
1.3 0.5 0.2 0.0
2.8 1.0 1.0 2.6 4.9 6.3 4.5 4.5 6.8 8.2 6.0 3.1 3.1
All timing parameters are described in Tables 14 through 20 in this data sheet.
Altera Corporation
59
FLEX 10K Embedded Programmable Logic Family Data Sheet
EPF10K10 & EPF10K20 Device EAB Internal Microparameters
Symbol -3 Speed Grade Min
tEABDATA1 tEABDATA2 tEABWE1 tEABWE2 tEABCLK tEABCO tEABBYPASS tEABSU tEABH tAA tWP tWDSU tWDH tWASU tWAH tWO tDD tEABOUT tEABCH tEABCL
Note:
(1)
Note (1)
-4 Speed Grade Min Max
1.9 6.0 1.2 6.2 2.2 0.6 1.9 1.8 2.5 ns ns ns ns ns ns ns ns ns 10.7 7.2 2.0 0.4 0.6 1.2 ns ns ns ns ns ns 6.2 6.2 0.6 4.0 7.2 ns ns ns ns ns
Unit
Max
1.5 4.8 1.0 5.0 1.0 0.5 1.5
1.5 2.0 8.7 5.8 1.6 0.3 0.5 1.0 5.0 5.0 0.5 4.0 5.8
All timing parameters are described in Tables 14 through 20 in this data sheet.
60
Altera Corporation
FLEX 10K Embedded Programmable Logic Family Data Sheet
EPF10K10 & EPF10K20 Device EAB Internal Timing Macroparameters
Symbol -3 Speed Grade Min
tEABAA tEABRCCOMB tEABRCREG tEABWP tEABWCCOMB tEABWCREG tEABDD tEABDATACO tEABDATASU tEABDATAH tEABWESU tEABWEH tEABWDSU tEABWDH tEABWASU tEABWAH tEABWO
Note:
(1)
Note (1)
-4 Speed Grade Unit
Max
13.7
Min
17.0 11.9 7.2 9.0 16.0
Max
17.0 ns ns ns ns ns ns 12.5 3.4 ns ns ns ns ns ns ns ns ns ns 11.8 ns
13.7 9.7 5.8 7.3 13.0 10.0 2.0 5.3 0.0 5.5 0.0 5.5 0.0 2.1 0.0 9.5
5.6 0.0 5.8 0.0 5.8 0.0 2.7 0.0
All timing parameters are described in Tables 14 through 20 in this data sheet.
Altera Corporation
61
FLEX 10K Embedded Programmable Logic Family Data Sheet
EPF10K10 Device Interconnect Timing Microparameters
Symbol -3 Speed Grade Min
tDIN2IOE tDIN2LE tDIN2DATA tDCLK2IOE tDCLK2LE tSAMELAB tSAMEROW tSAMECOLUMN tDIFFROW tTWOROWS tLEPERIPH tLABCARRY tLABCASC
Note (1)
-4 Speed Grade Min Max
6.2 3.8 5.2 4.0 3.8 0.6 3.8 1.1 4.9 8.7 3.9 0.8 3.0 ns ns ns ns ns ns ns ns ns ns ns ns ns
Unit
Max
4.8 2.6 4.3 3.4 2.6 0.6 3.6 0.9 4.5 8.1 3.3 0.5 2.7
EPF10K20 Device Interconnect Timing Microparameters
Symbol -3 Speed Grade Min
tDIN2IOE tDIN2LE tDIN2DATA tDCLK2IOE tDCLK2LE tSAMELAB tSAMEROW tSAMECOLUMN tDIFFROW tTWOROWS tLEPERIPH tLABCARRY tLABCASC
Note to tables:
(1)
Note (1)
-4 Speed Grade Min Max
6.6 3.8 5.2 4.0 3.8 0.6 3.9 1.6 5.5 9.4 5.6 0.8 3.0 ns ns ns ns ns ns ns ns ns ns ns ns ns
Unit
Max
5.2 2.6 4.3 4.3 2.6 0.6 3.7 1.4 5.1 8.8 4.7 0.5 2.7
All timing parameters are described in Tables 14 through 20 in this data sheet.
62
Altera Corporation
FLEX 10K Embedded Programmable Logic Family Data Sheet
EPF10K10 & EPF10K20 Device External Timing Parameters
Symbol -3 Speed Grade Min
tDRR tINSU, Notes (2), (3) tINH, Note (3) tOUTCO, Note (3) tODH, Note (3) Notes:
(1) (2) (3)
Note (1)
-4 Speed Grade Min
6.0 0.0
Unit
Max
16.1
Max
20.0 ns ns ns 8.4 ns ns
5.5 0.0 6.7 2.0
2.0
All timing parameters are described in Tables 14 through 20 in this data sheet. Using an LE to register the signal may provide a lower setup time. This parameter is specified by characterization.
EPF10K10A Device External Timing Parameters EPF10K10 Device External Timing Parameters
Symbol -1 Speed Grade Min
tDRR Notes:
(1) (2) All timing parameters are described in Tables 14 through 20 in this data sheet. These timing parameters are preliminary. For the most up-to-date information, contact Altera Applications at (800) 800-EPLD.
(1), (2)
-2 Speed Grade Min Max
10.4
-2 Speed Grade Min Max
12.2
Unit
Max
9.0
ns
Altera Corporation
63
FLEX 10K Embedded Programmable Logic Family Data Sheet
EPF10K30, EPF10K40 & EPF10K50 Device Internal & External Timing Parameters EPF10K30, EPF10K40 & EPF10K50 Device LE Timing Microparameters
Symbol -3 Speed Grade Min
tLUT tCLUT tRLUT tPACKED tEN tCICO tCGEN tCGENR tCASC tC tCO tCOMB tSU tH tPRE tCLR tCH tCL
Note:
(1) All timing parameters are described in Tables 14 through 20 in this data sheet.
Note (1)
Unit
-4 Speed Grade Min Max
1.8 0.6 2.0 0.8 1.5 0.4 1.4 1.4 1.2 1.6 1.2 0.6 1.4 1.3
Max
1.3 0.6 1.5 0.5 0.9 0.2 0.9 0.9 1.0 1.3 0.9 0.6
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1.4 0.9 0.9 0.9 4.0 4.0
1.2 1.2 4.0 4.0
ns ns ns ns
64
Altera Corporation
FLEX 10K Embedded Programmable Logic Family Data Sheet
EPF10K30, EPF10K40 & EPF10K50 Device IOE Timing Microparameters
Symbol
tIOD tIOC tIOCO tIOCOMB tIOSU tIOH tIOCLR tOD1 tOD2 tOD3 tXZ tZX1 tZX2 tZX3 tINREG tIOFD tINCOMB
Note:
(1) All timing parameters are described in Tables 14 through 20 in this data sheet.
Note (1)
Unit
ns ns ns ns ns ns 1.2 3.6 6.5 8.3 5.5 5.5 8.4 10.2 10.0 4.0 4.0 ns ns ns ns ns ns ns ns ns ns ns
-3 Speed Grade Min Max
0.4 0.5 0.4 0.0 3.1 1.0 1.0 3.3 5.6 7.0 5.2 5.2 7.5 8.9 7.7 3.3 3.3
-4 Speed Grade Min Max
0.6 0.9 0.5 0.0 3.5 1.9
Altera Corporation
65
FLEX 10K Embedded Programmable Logic Family Data Sheet
EPF10K30, EPF10K40 & EPF10K50 Device EAB Internal Microparameters
Symbol -3 Speed Grade Min
tEABDATA1 tEABDATA2 tEABWE1 tEABWE2 tEABCLK tEABCO tEABBYPASS tEABSU tEABH tAA tWP tWDSU tWDH tWASU tWAH tWO tDD tEABOUT tEABCH tEABCL
Note:
(1) All timing parameters are described in Tables 14 through 20 in this data sheet.
Note (1)
Unit
-4 Speed Grade Min Max
1.9 6.0 1.2 6.2 2.2 0.6 1.9 1.8 2.5
Max
1.5 4.8 1.0 5.0 1.0 0.5 1.5
ns ns ns ns ns ns ns ns ns
1.5 2.0 8.7 5.8 1.6 0.3 0.5 1.0 5.0 5.0 0.5 4.0 5.8
10.7 7.2 2.0 0.4 0.6 1.2 6.2 6.2 0.6 4.0 7.2
ns ns ns ns ns ns ns ns ns ns ns
66
Altera Corporation
FLEX 10K Embedded Programmable Logic Family Data Sheet
EPF10K30, EPF10K40 & EPF10K50 Device EAB Internal Timing Macroparameters
Symbol -3 Speed Grade Min
tEABAA tEABRCCOMB tEABRCREG tEABWP tEABWCCOMB tEABWCREG tEABDD tEABDATACO tEABDATASU tEABDATAH tEABWESU tEABWEH tEABWDSU tEABWDH tEABWASU tEABWAH tEABWO
Note:
(1) All timing parameters are described in Tables 14 through 20 in this data sheet.
Note (1)
Unit
-4 Speed Grade Min
17.0 11.9 7.2 9.0 16.0
Max
13.7
Max
17.0 ns ns ns ns ns ns 12.5 3.4 ns ns ns ns ns ns ns ns ns ns 11.8 ns
13.7 9.7 5.8 7.3 13.0 10.0 2.0 5.3 0.0 5.5 0.0 5.5 0.0 2.1 0.0 9.5
5.6 0.0 5.8 0.0 5.8 0.0 2.7 0.0
Altera Corporation
67
FLEX 10K Embedded Programmable Logic Family Data Sheet
EPF10K30 Device Interconnect Timing Microparameters
Symbol -3 Speed Grade Min
tDIN2IOE tDIN2LE tDIN2DATA tDCLK2IOE tDCLK2LE tSAMELAB tSAMEROW tSAMECOLUMN tDIFFROW tTWOROWS tLEPERIPH tLABCARRY tLABCASC
Note (1)
-4 Speed Grade Min Max
8.7 4.8 7.2 6.2 4.8 0.3 3.7 2.7 6.4 10.1 7.1 0.6 3.0 ns ns ns ns ns ns ns ns ns ns ns ns ns
Unit
Max
6.9 3.6 5.5 4.6 3.6 0.3 3.3 2.5 5.8 9.1 6.2 0.4 2.4
EPF10K40 Device Interconnect Timing Microparameters
Symbol -3 Speed Grade Min
tDIN2IOE tDIN2LE tDIN2DATA tDCLK2IOE tDCLK2LE tSAMELAB tSAMEROW tSAMECOLUMN tDIFFROW tTWOROWS tLEPERIPH tLABCARRY tLABCASC
Note to tables:
(1)
Note (1)
-4 Speed Grade Min Max
9.4 4.8 7.2 6.2 4.8 0.3 3.7 3.2 6.4 10.6 7.1 0.6 3.0 ns ns ns ns ns ns ns ns ns ns ns ns ns
Unit
Max
7.6 3.6 5.5 4.6 3.6 0.3 3.3 3.1 6.4 9.7 6.4 0.4 2.4
All timing parameters are described in Tables 14 through 20 in this data sheet.
68
Altera Corporation
FLEX 10K Embedded Programmable Logic Family Data Sheet
EPF10K50 Device Interconnect Timing Microparameters
Symbol -3 Speed Grade Min
tDIN2IOE tDIN2LE tDIN2DATA tDCLK2IOE tDCLK2LE tSAMELAB tSAMEROW tSAMECOLUMN tDIFFROW tTWOROWS tLEPERIPH tLABCARRY tLABCASC
Note (1)
-4 Speed Grade Min Max
10.2 4.8 7.2 6.2 4.8 0.3 3.7 4.1 7.8 11.5 8.2 0.6 3.0 ns ns ns ns ns ns ns ns ns ns ns ns ns
Unit
Max
8.4 3.6 5.5 4.6 3.6 0.3 3.3 3.9 7.2 10.5 7.5 0.4 2.4
EPF10K30, EPF10K40 & EPF10K50 Device External Timing Parameters
Symbol -3 Speed Grade Min
tDRR tINSU, Notes (2), (3) tINH, Note (3) tOUTCO, Note (3) tODH, Note (3) Notes to tables:
(1) (2) (3) All timing parameters are described in Tables 14 through 20 in this data sheet. Using an LE to register the signal may provide a lower setup time. This parameter is specified by characterization.
Note (1)
Unit
-4 Speed Grade Min
6.4 0.0 8.8 11.2 2.0
Max
17.2
Max
21.1 ns ns ns ns ns
5.7 0.0 2.0
Altera Corporation
69
FLEX 10K Embedded Programmable Logic Family Data Sheet
EPF10K70 Device Internal & External Timing Parameters EPF10K70 Device LE Timing Microparameters
Symbol -2 Speed Grade, Note (2) Min
tLUT tCLUT tRLUT tPACKED tEN tCICO tCGEN tCGENR tCASC tC tCO tCOMB tSU tH tPRE tCLR tCH tCL
Notes:
(1) (2) All timing parameters are described in Tables 14 through 20 in this data sheet. These parameters are preliminary. For the most up-to-date information, contact Altera Applications.
Note (1)
-3 Speed Grade Min Max
1.5 0.4 1.6 0.9 0.9 0.2 1.1 1.2 1.1 0.8 1.0 0.5 2.1 2.3 2.6 3.1 1.0 1.0 4.0 4.0 4.0 4.0 1.4 1.4
-4 Speed Grade Min Max
2.0 0.5 2.0 1.3 1.2 0.3 1.4 1.5 1.3 1.0 1.4 0.7
Unit
Max
1.3 0.4 1.5 0.8 0.8 0.2 1.0 1.1 1.0 0.7 0.9 0.4
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1.9 2.1 0.9 0.9 4.0 4.0
70
Altera Corporation
FLEX 10K Embedded Programmable Logic Family Data Sheet
EPF10K70 Device IOE Timing Microparameters
Symbol
tIOD tIOC tIOCO tIOCOMB tIOSU tIOH tIOCLR tOD1 tOD2 tOD3 tXZ tZX1 tZX2 tZX3 tINREG tIOFD tINCOMB
Notes:
(1) (2)
Note (1)
-3 Speed Grade Min Max
0.0 0.5 0.4 0.0 5.0 0.5 6.2 0.7 0.7 4.0 6.3 7.7 6.2 6.2 8.5 9.9 9.0 8.1 8.1 1.6 5.0 7.3 8.7 6.8 6.8 9.1 10.5 10.2 10.3 10.3
-2 Speed Grade, Note (2) Min Max
0.0 0.4 0.4 0.0 4.5 0.4 0.6 3.6 5.6 6.9 5.5 5.5 7.5 8.8 8.0 7.2 7.2
-4 Speed Grade Min Max
0.0 0.7 0.9 0.0
Unit
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
All timing parameters are described in Table 14 through 20 in this data sheet. These parameters are preliminary. For the most up-to-date information, contact Altera Applications.
Altera Corporation
71
FLEX 10K Embedded Programmable Logic Family Data Sheet
EPF10K70 Device EAB Internal Microparameters
Symbol -2 Speed Grade, Note (2) Min
tEABDATA1 tEABDATA2 tEABWE1 tEABWE2 tEABCLK tEABCO tEABBYPASS tEABSU tEABH tAA tWP tWDSU tWDH tWASU tWAH tWO tDD tEABOUT tEABCH tEABCL
Notes:
(1) (2)
Note (1)
-3 Speed Grade Min Max
1.5 4.8 1.0 5.0 1.0 0.5 1.5 1.5 2.0 1.8 2.5 8.7 5.8 1.6 0.3 0.5 1.0 7.2 2.0 0.4 0.6 1.2 5.0 5.0 0.5 4.0 4.0 4.0 4.0 6.2 6.2 0.6 10.7
-4 Speed Grade Min Max
1.9 6.0 1.2 6.2 2.2 0.6 1.9
Unit
Max
1.3 4.3 0.9 4.5 0.9 0.4 1.3
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1.3 1.8 7.8 5.2 1.4 0.3 0.4 0.9 4.5 4.5 0.4 4.0 4.0
All timing parameters are described in Tables 14 through 20 in this data sheet. These parameters are preliminary. For the most up-to-date information, contact Altera Applications.
72
Altera Corporation
FLEX 10K Embedded Programmable Logic Family Data Sheet
EPF10K70 Device EAB Internal Timing Macroparameters
Symbol -2 Speed Grade, Note (2) Min
tEABAA tEABRCCOMB tEABRCREG tEABWP tEABWCCOMB tEABWCREG tEABDD tEABDATACO tEABDATASU tEABDATAH tEABWESU tEABWEH tEABWDSU tEABWDH tEABWASU tEABWAH tEABWO
Notes:
(1) (2)
Note (1)
-4 Speed Grade Min
17.0 11.9 7.2 9.0 16.0 10.0 2.0 12.5 3.4 5.6 0.0 5.8 0.0 2.7 0.0 5.8 0.0 9.5 11.8
-3 Speed Grade Min
13.7 9.7 5.8 7.3 13.0
Unit
Max
12.1
Max
13.7
Max
17.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
12.1 8.6 5.2 6.5 11.6 8.8 1.7 4.7 0.0 4.9 0.0 1.8 0.0 4.1 0.0 8.4
5.3 0.0 5.5 0.0 2.1 0.0 4.7 0.0
All timing parameters are described in Tables 14 through 20 in this data sheet. These parameters are preliminary. For the most up-to-date information, contact Altera Applications.
Altera Corporation
73
FLEX 10K Embedded Programmable Logic Family Data Sheet
EPF10K70 Device Interconnect Timing Microparameters
Symbol -2 Speed Grade, Note (2) Min
tDIN2IOE tDIN2LE tDIN2DATA tDCLK2IOE tDCLK2LE tSAMELAB tSAMEROW tSAMECOLUMN tDIFFROW tTWOROWS tLEPERIPH tLABCARRY tLABCASC
Notes:
(1) (2)
Note (1)
-4 Speed Grade Min Max
8.8 6.0 10.8 7.7 6.0 0.5 5.5 3.7 9.2 14.7 6.5 1.1 3.2 ns ns ns ns ns ns ns ns ns ns ns ns ns
-3 Speed Grade Min Max
7.3 4.8 7.1 6.2 4.8 0.4 4.9 3.4 8.3 13.2 5.7 0.9 3.0
Unit
Max
6.6 4.2 6.5 5.5 4.2 0.4 4.8 3.3 8.1 12.9 5.5 0.8 2.7
All timing parameters are described in Tables 14 through 20 in this data sheet. These parameters are preliminary. For the most up-to-date information, contact Altera Applications.
EPF10K70 Device External Timing Parameters
Symbol -2 Speed Grade, Note (2) Min
tDRR tINSU, Notes (3), (4) tINH, Note (4) tOUTCO, Note (4) tODH, Note (4) Notes:
(1) (2) (3) (4)
Note (1)
-3 Speed Grade Min
7.3 0.0
-4 Speed Grade Min
8.0 0.0
Unit
Max
17.2
Max
19.1
Max
24.2 ns ns ns 14.3 ns ns
6.6 0.0 9.9 2.0
11.1 2.0 2.0
All timing parameters are described in Tables 14 through 20 in this data sheet. These parameters are preliminary. For the most up-to-date information, contact Altera Applications. Using an LE to register the signal may provide a lower setup time. This parameter is specified by characterization.
74
Altera Corporation
FLEX 10K Embedded Programmable Logic Family Data Sheet
EPF10K100 Device Internal & External Timing Parameters EPF10K100 Device LE Timing Microparameters
Symbol -3DX Speed Grade Min
tLUT tCLUT tRLUT tPACKED tEN tCICO tCGEN tCGENR tCASC tC tCO tCOMB tSU tH tPRE tCLR tCH tCL
Note:
(1) All timing parameters are described in Tables 14 through 20 in this data sheet.
Note (1)
-3 Speed Grade Min Max
1.5 0.4 1.6 0.9 0.9 0.2 1.1 1.2 1.1 0.8 1.0 0.5 2.1 2.3 2.6 3.1 1.0 1.0 4.0 4.0 4.0 4.0 1.4 1.4
-4 Speed Grade Min Max
2.0 0.5 2.0 1.3 1.2 0.3 1.4 1.5 1.3 1.0 1.4 0.7
Unit
Max
1.5 0.4 1.6 0.9 0.9 0.2 1.1 1.2 1.1 0.8 1.0 0.5
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
2.1 2.3 1.0 1.0 4.0 4.0
Altera Corporation
75
FLEX 10K Embedded Programmable Logic Family Data Sheet
EPF10K100 Device IOE Timing Microparameters
Symbol -3DX Speed Grade Min
tIOD tIOC tIOCO tIOCOMB tIOSU tIOH tIOCLR tOD1 tOD2 tOD3 tXZ tZX1 tZX2 tZX3 tINREG without ClockLock or ClockBoost circuitry tINREG with ClockLock or ClockBoost circuitry tIOFD tINCOMB
Note:
(1)
Note (1)
-3 Speed Grade Min Max
0.0 0.5 0.4 0.0 5.5 0.5 6.7 0.7 0.7 4.0 6.3 7.7 6.2 6.2 8.5 9.9 9.0 - 8.1 8.1 1.6 5.0 7.3 8.7 6.8 6.8 9.1 10.5 10.5 - 10.3 10.3
-4 Speed Grade Min Max
0.0 0.7 0.9 0.0
Unit
Max
0.0 0.5 0.4 0.0
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
5.5 0.5 0.7 4.0 6.3 7.7 6.2 6.2 8.5 9.9 9.0 3.0 8.1 8.1
All timing parameters are described in Tables 14 through 20 in this data sheet.
76
Altera Corporation
FLEX 10K Embedded Programmable Logic Family Data Sheet
EPF10K100 Device EAB Internal Microparameters
Symbol -3DX Speed Grade Min
tEABDATA1 tEABDATA2 tEABWE1 tEABWE2 tEABCLK tEABCO tEABBYPASS tEABSU tEABH tAA tWP tWDSU tWDH tWASU tWAH tWO tDD tEABOUT tEABCH tEABCL
Note:
(1)
Note (1)
-3 Speed Grade Min Max
1.5 4.8 1.0 5.0 1.0 0.5 1.5 1.5 2.0 1.8 2.5 8.7 5.8 1.6 0.3 0.5 1.0 7.2 2.0 0.4 0.6 1.2 5.0 5.0 0.5 4.0 5.8 4.0 7.2 6.2 6.2 0.6 10.7
-4 Speed Grade Min Max
1.9 6.0 1.2 6.2 2.2 0.6 1.9
Unit
Max
1.5 4.8 1.0 5.0 1.0 0.5 1.5
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1.5 2.0 8.7 5.8 1.6 0.3 0.5 1.0 5.0 5.0 0.5 4.0 5.8
All timing parameters are described in Tables 14 through 20 in this data sheet.
Altera Corporation
77
FLEX 10K Embedded Programmable Logic Family Data Sheet
EPF10K100 Device EAB Internal Timing Macroparameters
Symbol -3DX Speed Grade Min
tEABAA tEABRCCOMB tEABRCREG tEABWP tEABWCCOMB tEABWCREG tEABDD tEABDATACO tEABDATASU tEABDATAH tEABWESU tEABWEH tEABWDSU tEABWDH tEABWASU tEABWAH tEABWO
Note:
(1)
Note (1)
-4 Speed Grade Min
17.0 11.9 7.2 9.0 16.0 10.0 2.0 12.5 3.4 5.6 0.0 5.8 0.0 5.8 0.0 2.7 0.0 9.5 11.8
-3 Speed Grade Min
13.7 9.7 5.8 7.3 13.0
Unit
Max
13.7
Max
13.7
Max
17.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
13.7 9.7 5.8 7.3 13.0 10.0 2.0 5.3 0.0 5.5 0.0 5.5 0.0 2.1 0.0 9.5
5.3 0.0 5.5 0.0 5.5 0.0 2.1 0.0
All timing parameters are described in Tables 14 through 20 in this data sheet.
78
Altera Corporation
FLEX 10K Embedded Programmable Logic Family Data Sheet
EPF10K100 Device Interconnect Timing Microparameters
Symbol -3 Speed Grade Min
tDIN2IOE tDIN2LE tDIN2DATA tDCLK2IOE without ClockLock or ClockBoost circuitry tDCLK2IOE with ClockLock or ClockBoost circuitry tDCLK2LE without ClockLock or ClockBoost circuitry tDCLK2LE with ClockLock or ClockBoost circuitry tSAMELAB tSAMEROW tSAMECOLUMN tDIFFROW tTWOROWS tLEPERIPH tLABCARRY tLABCASC
Note:
(1)
Note (1)
-4 Speed Grade Min Max
10.3 4.8 7.3 6.2 - 4.8 - 0.4 4.9 5.1 10.0 14.9 6.9 0.9 3.0
-3 Speed Grade Min Max
12.2 6.0 11.0 7.7 - 6.0 - 0.5 5.5 5.4 10.9 16.4 8.1 1.1 3.2
Unit
Max
10.3 4.8 7.3 6.2 2.3 4.8 2.3 0.4 4.9 5.1 10.0 14.9 6.9 0.9 3.0
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
All timing parameters are described in Tables 14 through 20 in this data sheet.
Altera Corporation
79
FLEX 10K Embedded Programmable Logic Family Data Sheet
EPF10K100 Device External Timing Parameters
Symbol
Note (1)
-3 Speed Grade Min Max
19.1 7.8 8.5
-3DX Speed Grade Min Max
19.1 7.8 6.2 0.0 11.1 6.7 2.0
-4 Speed Grade Min Max
24.2
Unit
tDRR tINSU, without ClockLock or ClockBoost circuitry Notes (2), (3) tINSU, with ClockLock or ClockBoost circuitry Notes (2), (3) tINH, Note (3) tOUTCO, without ClockLock or ClockBoost circuitry Notes (3) tOUTCO, with ClockLock or ClockBoost circuitry Note (3) tODH, Note (3) Notes:
(1) (2) (3)
ns ns ns
0.0 11.1
0.0 14.3
ns ns ns
2.0
2.0
ns
All timing parameters are described in Tables 14 through 20 in this data sheet. Using an LE to register the signal may provide a lower setup time. This parameter is specified by characterization.
80
Altera Corporation
FLEX 10K Embedded Programmable Logic Family Data Sheet
EPF10K50V Device Internal & External Timing Parameters EPF10K50V Device LE Timing Microparameters
Symbol -2 Speed Grade, Note (2) Min
tLUT tCLUT tRLUT tPACKED tEN tCICO tCGEN tCGENR tCASC tC tCO tCOMB tSU tH tPRE tCLR tCH tCL
Notes:
(1) (2) All timing parameters are described in Tables 14 through 20 in this data sheet. These parameters are preliminary. For the most up-to-date information, contact Altera Applications.
Note (1)
-3 Speed Grade -4 Speed Grade Min Max
1.6 0.6 1.0 0.7 1.4 0.3 1.2 0.4 0.9 1.5 1.0 0.6 2.5 1.4 0.5 0.5 4.0 4.0 4.0 4.0 0.5 0.5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Unit
Max
1.0 0.5 0.8 0.4 0.9 0.2 0.7 0.3 0.7 1.0 0.7 0.4
Min
Max
1.3 0.6 0.9 0.5 1.1 0.2 0.8 0.3 0.8 1.3 0.9 0.5
1.6 0.8 0.4 0.4 4.0 4.0
2.2 1.0
Altera Corporation
81
FLEX 10K Embedded Programmable Logic Family Data Sheet
EPF10K50V Device IOE Timing Microparameters
Symbol -2 Speed Grade, Note (2) Min
tIOD tIOC tIOCO tIOCOMB tIOSU tIOH tIOCLR tOD1 tOD2 tOD3 tXZ tZX1 tZX2 tZX3 tINREG tIOFD tINCOMB
Notes:
(1) (2)
Note (1)
-4 Speed Grade Min Max
2.1 0.5 0.4 0.0 3.9 1.4 0.7 3.9 - 7.6 3.8 3.8 - 7.5 7.0 2.3 2.3 0.7 4.7 - 8.4 4.6 4.6 - 8.3 9.0 2.7 2.7 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
-3 Speed Grade Min Max
1.9 0.5 0.4 0.0 3.4 1.0
Unit
Max
1.6 0.4 0.3 0.0
2.8 0.8 0.6 3.2 - 6.9 3.1 3.1 - 6.8 5.7 1.9 1.9
All timing parameters are described in Tables 14 through 20 in this data sheet. These parameters are preliminary. For the most up-to-date information, contact Altera Applications.
82
Altera Corporation
FLEX 10K Embedded Programmable Logic Family Data Sheet
EPF10K50V Device EAB Internal Microparameters
Symbol -2 Speed Grade, Note (2) Min
tEABDATA1 tEABDATA2 tEABWE1 tEABWE2 tEABCLK tEABCO tEABBYPASS tEABSU tEABH tAA tWP tWDSU tWDH tWASU tWAH tWO tDD tEABOUT tEABCH tEABCL
Notes:
(1) (2)
Note (1)
-4 Speed Grade Min Max
4.6 5.9 3.7 6.2 1.2 0.4 1.6 2.2 2.5 10.0 12.4 7.4 1.2 0.4 0.6 1.2 5.3 5.3 0.5 6.5 6.5 0.6 4.0 4.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
-3 Speed Grade Min Max
3.4 4.8 3.0 5.0 1.0 0.3 1.3 1.8 2.0
Unit
Max
2.8 3.9 2.5 4.1 0.8 0.2 1.1
1.5 1.6 8.2 4.9 0.8 0.2 0.4 0.8 4.3 4.3 0.4 4.0 4.0
6.0 1.0 0.3 0.5 1.0
4.0 4.0
All timing parameters are described in Tables 14 through 20 in this data sheet. These parameters are preliminary. For the most up-to-date information, contact Altera Applications.
Altera Corporation
83
FLEX 10K Embedded Programmable Logic Family Data Sheet
EPF10K50V Device EAB Internal Timing Macroparameters
Symbol -2 Speed Grade, Note (2) Min
tEABAA tEABRCCOMB tEABRCREG tEABWP tEABWCCOMB tEABWCREG tEABDD tEABDATACO tEABDATASU tEABDATAH tEABWESU tEABWEH tEABWDSU tEABWDH tEABWASU tEABWAH tEABWO
Notes:
(1) (2)
Note (1)
-4 Speed Grade Min
20.8 13.4 7.4 9.2 17.4 11.8 1.8 14.9 2.2 6.9 0.0 7.2 0.0 2.1 0.0 7.4 0.0 11.4 14.0
-3 Speed Grade Min
16.5 10.8 6.0 7.5 14.2
Unit
Max
13.6
Max
16.5
Max
20.8 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
13.6 8.8 4.9 6.1 11.6 9.7 1.4 4.6 0.0 4.8 0.0 1.1 0.0 4.6 0.0 9.4
5.6 0.0 5.8 0.0 1.4 0.0 5.6 0.0
All timing parameters are described in Tables 14 through 20 in this data sheet. These parameters are preliminary. For the most up-to-date information, contact Altera Applications.
84
Altera Corporation
FLEX 10K Embedded Programmable Logic Family Data Sheet
EPF10K50V Device Interconnect Timing Microparameters
Symbol -2 Speed Grade, Note (2) Min
tDIN2IOE tDIN2LE tDIN2DATA tDCLK2IOE tDCLK2LE tSAMELAB tSAMEROW tSAMECOLUMN tDIFFROW tTWOROWS tLEPERIPH tLABCARRY tLABCASC
Note (1)
-4 Speed Grade Min Max
8.2 3.9 7.5 5.5 3.9 0.3 3.9 2.7 6.6 10.5 6.5 0.7 2.0 ns ns ns ns ns ns ns ns ns ns ns ns ns
-3 Speed Grade Min Max
7.2 3.1 6.6 4.8 3.1 0.3 4.3 3.4 7.7 12.0 5.7 0.5 1.6
Unit
Max
6.0 2.6 5.7 3.9 2.6 0.2 2.9 3.6 6.5 9.4 5.0 0.4 1.3
EPF10K50V Device External Timing Parameters
Symbol -1 Speed Grade, Note (2) Min
tDRR tINSU, Notes (3), (4) tINH, Note (4) tOUTCO, Note (4) tODH, Note (4) Notes:
(1) (2) (3) (4)
Note (1)
-3 Speed Grade Min
5.2 0.0 7.8 9.5 2.0 2.0
-2 Speed Grade, Note (3) Min
4.2 0.0 2.0
-4 Speed Grade Min
6.9 0.0 11.1
Unit
Max
11.2
Max
14.0
Max
17.2
Max
21.1 ns ns ns ns ns
All timing parameters are described in Tables 14 through 20 in this data sheet. The -1 speed grade is under development. Contact your local Altera sales representative for availability. These parameters are preliminary. For the most up-to-date information, contact Altera Applications at (800) 800-EPLD. This parameter is specified by characterization.
Altera Corporation
85
FLEX 10K Embedded Programmable Logic Family Data Sheet
EPF10K130V Device Internal & External Timing Parameters EPF10K130V Device LE Timing Microparameters
Symbol -2 Speed Grade Min
tLUT tCLUT tRLUT tPACKED tEN tCICO tCGEN tCGENR tCASC tC tCO tCOMB tSU tH tPRE tCLR tCH tCL
Notes:
(1) (2) All timing parameters are described in Tables 14 through 20 in this data sheet. These parameters are preliminary. For the most up-to-date information, contact Altera Applications.
Notes (1), (2)
-3 Speed Grade Min Max
1.8 0.7 1.7 0.6 0.8 0.3 0.4 1.0 1.2 2.4 0.9 0.7 0.2 0.0 0.3 0.0 3.1 3.1 4.0 4.0 4.0 4.0 3.9 3.9
-4 Speed Grade Min Max
2.3 0.9 2.2 0.7 1.0 0.4 0.5 1.3 1.5 3.0 1.1 0.9
Unit
Max
1.3 0.5 1.2 0.5 0.6 0.2 0.3 0.7 0.9 1.9 0.6 0.5
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
0.2 0.0 2.4 2.4 4.0 4.0
86
Altera Corporation
FLEX 10K Embedded Programmable Logic Family Data Sheet
EPF10K130V Device IOE Timing Microparameters
Symbol -2 Speed Grade Min
tIOD tIOC tIOCO tIOCOMB tIOSU tIOH tIOCLR tOD1 tOD2 tOD3 tXZ tZX1 tZX2 tZX3 tINREG tIOFD tINCOMB
Notes:
(1) (2)
Notes (1), (2)
-3 Speed Grade Min Max
1.6 0.5 0.4 0.0 3.3 0.0 3.8 0.0 2.2 4.4 - 8.1 6.3 6.3 - 10.0 10.0 7.9 7.9 2.7 5.0 - 9.7 7.4 7.4 - 12.1 12.6 9.9 9.9
-4 Speed Grade Min Max
2.0 0.7 0.5 0.0
Unit
Max
1.3 0.4 0.3 0.0
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
2.6 0.0 1.7 3.5 - 8.2 4.9 4.9 - 9.6 7.9 6.2 6.2
All timing parameters are described in Tables 14 through 20 in this data sheet. These parameters are preliminary. For the most up-to-date information, contact Altera Applications.
Altera Corporation
87
FLEX 10K Embedded Programmable Logic Family Data Sheet
EPF10K130V Device EAB Internal Microparameters
Symbol -2 Speed Grade Min
tEABDATA1 tEABDATA2 tEABWE1 tEABWE2 tEABCLK tEABCO tEABBYPASS tEABSU tEABH tAA tWP tWDSU tWDH tWASU tWAH tWO tDD tEABOUT tEABCH tEABCL
Notes:
(1) (2)
Note (1), (2)
-3 Speed Grade Min Max
2.4 4.7 2.4 4.7 0.9 0.6 0.8 1.8 0.0 1.8 0.0 7.1 4.7 5.9 0.0 5.0 0.0 4.7 5.9 0.0 5.0 0.0 7.1 7.1 3.1 4.0 4.7 4.0 4.7 7.1 7.1 3.1 7.1
-4 Speed Grade Min Max
2.4 4.7 2.4 4.7 0.9 0.6 0.8
Unit
Max
1.9 3.7 1.9 3.7 0.7 0.5 0.6
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1.4 0.0 5.6 3.7 4.6 0.0 3.9 0.0 5.6 5.6 2.4 4.0 4.0
All timing parameters are described in Tables 14 through 20 in this data sheet. These parameters are preliminary. For the most up-to-date information, contact Altera Applications.
88
Altera Corporation
FLEX 10K Embedded Programmable Logic Family Data Sheet
EPF10K130V Device EAB Internal Timing Macroparameters
Symbol -2 Speed Grade Min
tEABAA tEABRCCOMB tEABRCREG tEABWP tEABWCCOMB tEABWCREG tEABDD tEABDATACO tEABDATASU tEABDATAH tEABWESU tEABWEH tEABWDSU tEABWDH tEABWASU tEABWAH tEABWO
Notes:
(1) (2)
Notes (1), (2)
-4 Speed Grade Min
14.2 10.8 4.7 9.7 17.8 14.2 4.6 14.2 4.6 5.6 0.0 5.6 0.0 5.9 0.0 5.0 0.0 14.2 14.2
-3 Speed Grade Min
14.2 10.8 4.7 9.7 17.8
Unit
Max
11.2
Max
14.2
Max
14.2 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
11.1 8.5 3.7 7.6 14.0 11.1 3.6 4.4 0.0 4.4 0.0 4.6 0.0 3.9 0.0 11.1
5.6 0.0 5.6 0.0 5.9 0.0 5.0 0.0
All timing parameters are described in Tables 14 through 20 in this data sheet. These parameters are preliminary. For the most up-to-date information, contact Altera Applications.
Altera Corporation
89
FLEX 10K Embedded Programmable Logic Family Data Sheet
EPF10K130V Device Interconnect Timing Microparameters
Symbol -2 Speed Grade Min
tDIN2IOE tDIN2LE tDIN2DATA tDCLK2IOE tDCLK2LE tSAMELAB tSAMEROW tSAMECOLUMN tDIFFROW tTWOROWS tLEPERIPH tLABCARRY tLABCASC
Notes (1), (2)
-4 Speed Grade Min Max
9.5 3.1 7.4 5.1 3.1 0.8 6.5 9.7 16.2 22.7 9.5 1.0 1.2 ns ns ns ns ns ns ns ns ns ns ns ns ns
-3 Speed Grade Min Max
9.0 3.0 6.3 4.6 3.0 0.6 5.3 9.5 14.8 20.1 8.6 0.8 1.0
Unit
Max
8.0 2.4 5.0 3.6 2.4 0.4 4.5 9.0 13.5 18.0 8.1 0.6 0.8
EPF10K130V Device External Timing Parameters
Symbol -2 Speed Grade Min
tDRR tINSU, Notes (3), (4) tINH, Note (4) tOUTCO, Note (4) tODH, Note (4) Notes to tables:
(1) (2) (3) (4)
Notes (1), (2)
-3 Speed Grade Min
8.6 0.0
-4 Speed Grade Min
11.0 0.0
Unit
Max
15.0
Max
19.1
Max
24.2 ns ns ns 11.3 ns ns
6.9 0.0 7.8 2.0
9.9 2.0 2.0
All timing parameters are described in Tables 14 through 20 in this data sheet. These parameters are preliminary. For the most up-to-date information, contact Altera Applications. Using an LE to register the signal may provide a lower setup time. This parameter is specified by characterization.
90
Altera Corporation
FLEX 10K Embedded Programmable Logic Family Data Sheet
EPF10K100A Device Internal & External Timing Parameters EPF10K100A Device LE Timing Microparameters
Symbol -1 Speed Grade Min
tLUT tCLUT tRLUT tPACKED tEN tCICO tCGEN tCGENR tCASC tC tCO tCOMB tSU tH tPRE tCLR tCH tCL
Notes:
(1) (2) All timing parameters are described in Tables 14 through 20 in this data sheet. These parameters are preliminary. For the most up-to-date information, contact Altera Applications.
Notes (1), (2)
-2 Speed Grade Min Max
1.2 0.9 1.6 0.5 0.7 0.2 0.4 0.7 0.9 1.0 0.3 0.7 1.0 0.5 1.2 0.5 0.3 0.3 3.5 3.5 3.5 3.5 0.4 0.4
-3 Speed Grade Min Max
1.4 1.1 1.9 0.5 0.8 0.3 0.6 0.8 1.0 1.2 0.3 0.8
Unit
Max
1.0 0.8 1.4 0.4 0.6 0.2 0.4 0.6 0.7 0.9 0.2 0.6
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
0.8 0.3 0.3 0.3 2.5 2.5
Altera Corporation
91
FLEX 10K Embedded Programmable Logic Family Data Sheet
EPF10K100A Device IOE Timing Microparameters
Symbol -1 Speed Grade Min
tIOD tIOC tIOCO tIOCOMB tIOSU tIOH tIOCLR tOD1 tOD2 tOD3 tXZ tZX1 tZX2 tZX3 tINREG tIOFD tINCOMB
Notes:
(1) (2)
Notes (1), (2)
-2 Speed Grade Min Max
2.9 0.3 0.2 0.6 1.7 0.2 1.8 0.3 1.2 2.6 5.3 7.9 3.1 3.1 5.8 8.4 6.1 5.5 5.5 1.4 3.0 6.1 9.3 3.7 3.7 6.8 10.0 7.2 6.4 6.4
-3 Speed Grade Min Max
3.4 0.4 0.3 0.7
Unit
Max
2.5 0.3 0.2 0.5
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1.3 0.2 1.0 2.2 4.5 6.8 2.7 2.7 5.0 7.3 5.3 4.7 4.7
All timing parameters are described in Tables 14 through 20 in this data sheet. These parameters are preliminary. For the most up-to-date information, contact Altera Applications.
92
Altera Corporation
FLEX 10K Embedded Programmable Logic Family Data Sheet
EPF10K100A Device EAB Internal Microparameters
Symbol -1 Speed Grade Min
tEABDATA1 tEABDATA2 tEABWE1 tEABWE2 tEABCLK tEABCO tEABBYPASS tEABSU tEABH tAA tWP tWDSU tWDH tWASU tWAH tWO tDD tEABOUT tEABCH tEABCL
Notes:
(1) (2)
Notes (1), (2)
-2 Speed Grade Min Max
2.1 3.7 0.9 2.7 0.9 1.1 0.3 1.5 0.5 1.8 0.5 4.8 3.7 2.8 0.2 0.2 0.0 4.4 3.3 0.3 0.3 0.0 3.9 3.9 0.3 3.5 4.0 4.0 4.0 4.6 4.6 0.4 5.6
-3 Speed Grade Min Max
2.4 4.4 1.1 3.1 1.1 1.4 0.4
Unit
Max
1.8 3.2 0.8 2.3 0.8 1.0 0.3
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1.3 0.4 4.1 3.2 2.4 0.2 0.2 0.0 3.4 3.4 0.3 2.5 4.0
All timing parameters are described in Tables 14 through 20 in this data sheet. These parameters are preliminary. For the most up-to-date information, contact Altera Applications.
Altera Corporation
93
FLEX 10K Embedded Programmable Logic Family Data Sheet
EPF10K100A Device EAB Internal Timing Macroparameters
Symbol -1 Speed Grade Min
tEABAA tEABRCCOMB tEABRCREG tEABWP tEABWCCOMB tEABWCREG tEABDD tEABDATACO tEABDATASU tEABDATAH tEABWESU tEABWEH tEABWDSU tEABWDH tEABWASU tEABWAH tEABWO
Notes:
(1) (2)
Notes (1), (2)
-3 Speed Grade Min
9.2 7.4 4.4 4.7 12.8 6.9 2.3 8.2 2.9 5.1 0.0 3.8 0.0 4.6 0.0 2.6 0.0 5.7 6.9
-2 Speed Grade Min
7.8 6.2 3.7 3.9 10.8
Unit
Max
6.8
Max
7.8
Max
9.2 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
6.8 5.4 3.2 3.4 9.4 6.1 2.1 3.7 0.0 2.8 0.0 3.4 0.0 1.9 0.0 5.1
4.3 0.0 3.3 0.0 4.0 0.0 2.3 0.0
All timing parameters are described in Tables 14 through 20 in this data sheet. These parameters are preliminary. For the most up-to-date information, contact Altera Applications.
94
Altera Corporation
FLEX 10K Embedded Programmable Logic Family Data Sheet
EPF10K100A Device Interconnect Timing Microparameters
Symbol -1 Speed Grade Min
tDIN2IOE tDIN2LE tDIN2DATA tDCLK2IOE tDCLK2LE tSAMELAB tSAMEROW tSAMECOLUMN tDIFFROW tTWOROWS tLEPERIPH tLABCARRY tLABCASC
Notes (1), (2)
-3 Speed Grade Min Max
6.0 2.7 2.9 3.5 2.7 0.1 1.9 7.4 9.3 11.2 4.5 0.3 0.6 ns ns ns ns ns ns ns ns ns ns ns ns ns
-2 Speed Grade Min Max
5.4 2.4 2.7 3.0 2.4 0.1 1.7 6.5 8.2 9.9 4.2 0.2 0.5
Unit
Max
4.8 2.0 2.4 2.6 2.0 0.1 1.5 5.5 7.0 8.5 3.9 0.2 0.4
EPF10K100A Device External Timing Parameters
Symbol -1 Speed Grade Min
tDRR tINSU, Notes (3), (4) tINH, Note (4) tOUTCO, Note (4) tODH, Note (4) Notes to tables:
(1) (2) (3) (4)
Notes (1), (2)
-2 Speed Grade Min
4.5 0.0
-3 Speed Grade Min
5.1 0.0
Unit
Max
12.5
Max
14.5
Max
17.0 ns ns ns 7.2 ns ns
3.7 0.0 5.3 2.0
6.1 2.0 2.0
All timing parameters are described in Tables 14 through 20 in this data sheet. These parameters are preliminary. For the most up-to-date information, contact Altera Applications. Using an LE to register the signal may provide a lower setup time. This parameter is specified by characterization.
Altera Corporation
95
FLEX 10K Embedded Programmable Logic Family Data Sheet
External Reference Timing Parameters
Symbol
tDRR
Note (1)
-2 Speed Grade -3 Speed Grade
Device
EPF10K10A EPF10K30A EPF10K100B EPF10K250A
-1 Speed Grade
Unit
ns ns ns ns
Min
Max
10.0 11.0 10.5 14.5
Min
Max
12.0 14.0 12.0 16.5
Min
Max
16.0 17.0 13.5 19.0
Note:
(1) These timing parameters are preliminary. For the most up-to-date information, contact Altera Applications at (800) 800-EPLD.
ClockLock & ClockBoost Timing Parameters
For the ClockLock and ClockBoost circuitry to function properly, the incoming clock must meet certain requirements. If these specifications are not met, the circuitry may not lock onto the incoming clock, which generates an erroneous clock within the device. The clock generated by the ClockLock and ClockBoost circuitry must also meet certain specifications. If the incoming clock meets these requirements during configuration, the ClockLock and ClockBoost circuitry will lock onto the clock during configuration. The circuit will be ready for use immediately after configuration. Figure 28 illustrates the incoming and generated clock specifications.
Figure 28. Specifications for the Incoming & Generated Clocks
The tI parameter refers to the nominal input clock period; the tO parameter refers to the nominal output clock period.
tCLK1
Input Clock
tINDUTY
tI fCLKDEV
tR
tF tOUTDUTY
tI
tI tINCLKSTB
ClockLockGenerated Clock
tO
tO + tJITTER
tO - tJITTER
Table 21 summarizes the ClockLock and ClockBoost parameters.
96
Altera Corporation
FLEX 10K Embedded Programmable Logic Family Data Sheet
Table 21. ClockLock & ClockBoost Parameters (Part 1 of 2)
Symbol
tR tF t INDUTY f CLK1 t CLK1 fCLK2 tCLK2
Input rise time Input fall time Input duty cycle Input clock frequency (ClockBoost clock multiplication factor equals 1) Input clock period (ClockBoost clock multiplication factor equals 1) Input clock frequency (ClockBoost clock multiplication factor equals 2) Input clock period (ClockBoost clock multiplication factor equals 2) 45 30 12.5 16 20
Parameter
Min
Typ
Max
2 2 55 80 33.3 50 62.5 1 0.5 100
Unit
ns ns
%
MHz ns MHz ns MHz MHz ps
f CLKDEV1 Input deviation from user specification in MAX+PLUS II, (ClockBoost clock multiplication factor equals 1), Note (1) f CLKDEV2 Input deviation from user specification in MAX+PLUS II, (ClockBoost clock multiplication factor equals 2), Note (1) t INCLKSTB Input clock stability (measured between adjacent clocks)
Table 21. ClockLock & ClockBoost Parameters (Part 2 of 2)
Symbol
t LOCK t JITTER
Parameter
Time required for ClockLock or ClockBoost to acquire lock, Note (2) Jitter on ClockLock or ClockBoost-generated clock, Note (3)
Min
Typ
Max
10 1
Unit
s ns %
tOUTDUTY Duty cycle for ClockLock or ClockBoost-generated clock
40
50
60
Notes:
(1) To implement the ClockLock and ClockBoost circuitry with the MAX+PLUS II software, designers must specify the input frequency. The MAX+PLUS II software tunes the PLL in the ClockLock and ClockBoost circuitry to this frequency. The f CLKDEV parameter specifies how much the incoming clock can differ from the specified frequency during device operation. Simulation does not reflect this parameter. During device configuration, the ClockLock and ClockBoost circuitry is configured before the rest of the device. If the incoming clock is supplied during configuration, the ClockLock and ClockBoost circuitry locks during configuration, because the tLOCK value is less than the time required for configuration. The tJITTER specification is measured under long-term observation.
(2)
(3)
Power Consumption
The supply power (P) for FLEX 10K devices can be calculated with the following equation: P = PINT + PIO = (I CCSTANDBY + ICCACTIVE) x VCC + PIO Typical I CCSTANDBY values are shown as I CC0 in the OFLEX 10K 5.0-V Device DC Operating ConditionsO table on pages 41, 44, and 46 of this data sheet. The ICCACTIVE value depends on the switching frequency and the application logic. This value is calculated based on the amount of current that each LE typically consumes. The PIO value, which depends on the device output load characteristics and switching frequency, can be calculated using the guidelines given in Application Note 74 (Evaluating Power for Altera Devices) in this data book.
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FLEX 10K Embedded Programmable Logic Family Data Sheet
1
Compared to the rest of the device, the embedded array consumes a negligible amount of power. Therefore, the embedded array can be ignored when calculating supply current.
The ICCACTIVE value is calculated with the following equation: A ICCACTIVE = K x fMAX x N x togLC x -------------------------MHz x LE The parameters in this equation are shown below: fMAX N togLC K = = = = Maximum operating frequency in MHz Total number of logic cells used in the device Average percent of logic cells toggling at each clock (typically 12.5%) Constant, shown in Table 22
Table 22. K Constant Values
Device
EPF10K10 EPF10K20 EPF10K30 EPF10K40 EPF10K50 EPF10K70 EPF10K100 EPF10K10A EPF10K30A EPF10K50V EPF10K130V EPF10K100A EPF10K100B EPF10K250A Note:
(1) This value is preliminary. For the most up-to-date information, contact Altera Applications.
K Value
82 89 88 92 95 85 88 25, Note (1) 23, Note (1) 45 29 29, Note (1) 19, Note (1) 42, Note (1)
This calculation provides an ICC estimate based on typical conditions with no output load. The actual ICC should be verified during operation because this measurement is sensitive to the actual pattern in the device and the environmental operating conditions.
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FLEX 10K Embedded Programmable Logic Family Data Sheet
In order to better reflect actual designs, the power model (and the constant K in the power calculation equations shown above) for continuous interconnect FLEX devices assumes that logic cells drive FastTrack Interconnect channels. In contrast, the power model of segmented FPGAs assumes that all logic cells drive only one short interconnect segment. This assumption may lead to inaccurate results, compared to measured power consumption for an actual design in a segmented interconnect FPGA. Figure shows the relationship between the current and operating frequency of FLEX 10K devices. For other FLEX 10KA devices, contact Altera Applications.
Altera Corporation
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FLEX 10K Embedded Programmable Logic Family Data Sheet
Figure 29. ICCACTIVE vs. Operating Frequency (Part 1 of 4)
EPF10K10
500
Note (1)
EPF10K20
1,000
ICC Supply Current (mA)
400 350 300 250 200 150 100 50
ICC Supply Current (mA)
0 15 30 45 60
450
900 800 700 600 500 400 300 200 100 0
Frequency (MHz)
15
30
45
60
Frequency (MHz)
EPF10K30
1,600 1,400 1,200 1,000 800 600 400 200 0
EPF10K30A
1,200
I CC Supply Current (mA)
ICC Supply Current (mA)
1,000 800 600 400 200 0
15
30
45
60
50
100
Frequency (MHz)
Frequency (MHz)
100
Altera Corporation
FLEX 10K Embedded Programmable Logic Family Data Sheet
Figure 29. ICCACTIVE vs. Operating Frequency (Part 2 of 4)
EPF10K40
2,500
Note (1)
EPF10K50
3,000
ICC Supply Current (mA)
ICC Supply Current (mA)
0
2,000
2,500
2,000
1,500
1,500
1,000
1,000
500
500 0
15
30
45
60
15
30
45
60
Frequency (MHz)
Frequency (MHz)
EPF10K50V
1,600
EPF10K70
3,500
ICC Supply Current (mA)
ICC Supply Current (mA)
0 20 40 60 80 100
1,400 1,200 1,000 800 600 400 200
3,000 2,500 2,000 1,500 1,000 500 0
Frequency (MHz)
15
30
45
60
Frequency (MHz)
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FLEX 10K Embedded Programmable Logic Family Data Sheet
Figure 29. ICCACTIVE vs. Operating Frequency (Part 3 of 4)
EPF10K100
4,500
Note (1)
EPF10K100A
2,000
ICC Supply Current (mA)
4,000 3,500 3,000 2,500 2,000 1,500 1,000 500 0
ICC Supply Current (mA)
1,500
1000
500
15
30
45
60
0
20
40
60
80
100
Frequency (MHz)
Frequency (MHz)
EPF10K100B
EPF10K130V
ICC Supply Current (mA)
I CC Supply Current (mA)
2,500 2,000 1,500 1,000 500
2,000
1,500
1,000
500
0
0
50
100
20
40
60
80
100
Frequency (MHz)
Frequency (MHz)
102
Altera Corporation
FLEX 10K Embedded Programmable Logic Family Data Sheet
Figure 29. ICCACTIVE vs. Operating Frequency (Part 4 of 4)
EPF10K250A I CC Supply Current (mA)
8,000 6,000 4,000 2,000
Note (1)
0
50
100
Frequency (MHz) Note:
(1) The information on EPF10K30A, EPF10K100B, and EPF10K250A devices are preliminary. Contact Altera Applications at (800) 800-EPLD for the most up-to-date information
Configuration & Operation f
The FLEX 10K architecture supports several configuration schemes. This section summarizes the device operating modes and available device configuration schemes. Go to AN 59 (Configuring FLEX 10K Devices) for detailed descriptions of device configuration options; device configuration pins; and information on configuring FLEX 10K devices, including sample schematics, timing diagrams, and configuration parameters.
Operating Modes
The FLEX 10K architecture uses SRAM configuration elements that require configuration data to be loaded every time the circuit powers up. The process of physically loading the SRAM data into the device is called configuration. During initialization, which occurs immediately after configuration, the device resets registers, enables I/O pins, and begins to operate as a logic device. The I/O pins are tri-stated during power-up, and before and during configuration. Together, the configuration and initialization processes are called command mode; normal device operation is called user mode.
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FLEX 10K Embedded Programmable Logic Family Data Sheet
SRAM configuration elements allow FLEX 10K devices to be reconfigured in-circuit by loading new configuration data into the device. Real-time reconfiguration is performed by forcing the device into command mode with a device pin, loading different configuration data, reinitializing the device, and resuming usermode operation. The entire reconfiguration process requires less than 320 ms and can be used to reconfigure an entire system dynamically. In-field upgrades can be performed by distributing new configuration files.
Programming Files
Despite being function- and pin- compatible, FLEX 10KA and FLEX 10KE devices are not programming- or configuration-file compatible with FLEX 10K devices. A design should be recompiled before it is transferred from a FLEX 10K device to an equivalent FLEX 10KA or FLEX 10KE device. This recompilation should be performed to create a new programming or configuration file and to check design timing on the faster FLEX 10KA or FLEX 10KE device. Although the programming or configuration files for the EPF10K50 device can program or configure a EPF10K50V device, Altera recommends recompiling a design with the EPF10K50V device when transferring a design from the EPF10K50 device.
Configuration Schemes
The configuration data for a FLEX 10K device can be loaded with one of five configuration schemes (see Table 23), chosen on the basis of the target application. An EPC1 or EPC1441 Configuration EPROM, intelligent controller, or the JTAG port can be used to control the configuration of a FLEX 10K device, allowing automatic configuration on system power-up. Multiple FLEX 10K devices can be configured in any of the five configuration schemes by connecting the configuration enable (nCE) and configuration enable output (nCEO) pins on each device.
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FLEX 10K Embedded Programmable Logic Family Data Sheet
Table 23. Data Sources for Configuration
Configuration Scheme
Configuration EPROM Passive serial (PS) Passive parallel asynchronous (PPA) Passive parallel synchronous (PPS) JTAG
Data Source
EPC1 or EPC1441 Configuration EPROM BitBlaster, ByteBlaster, or ByteBlasterMV download cable, or serial data source Parallel data source Parallel data source BitBlaster, ByteBlaster, or ByteBlasterMV download cable, or microprocessor with Jam File
Device Pin-Outs
Tables 24 through 26 show the pin names and numbers for the dedicated pins in each FLEX 10K device package.
Table 24. FLEX 10K Device Pin-Outs (Part 1 of 3)
Pin Name 84-Pin PLCC EPF10K10 144-Pin TQFP EPF10K10 EPF10K10A EPF10K20 EPF10K30A
Notes (1), (2)
208-Pin PQFP EPF10K10 EPF10K10A 208-Pin PQFP/ RQFP EPF10K20 EPF10K30 EPF10K30A EPF10K40 240-Pin 240-Pin PQFP/RQFP PQFP/RQFP EPF10K30A EPF10K20 EPF10K100A EPF10K30 EPF10K40 EPF10K50 EPF10K50V EPF10K70
124 123 60 121 179 2 26 178 3 238 236 240 239 23 11 190 188 124 123 60 121 179 2 26 178 3 238 236 240 239 23 11 190 188
MSEL0 (3) MSEL1 (3) nSTATUS (3) nCONFIG (3) DCLK (3) CONF_DONE (3) INIT_DONE (4) nCE (3) nCEO (3) nWS (5) nRS (5) nCS (5) CS (5) RDYnBSY (5) CLKUSR (5) DATA7 (5) DATA6 (5)
31 32 55 34 13 76 69 14 75 80 81 78 79 70 73 5 6
77 76 35 74 107 2 14 106 3 142 141 144 143 11 7 116 114
108 107 52 105 155 2 19 154 3 206 204 208 207 16 10 166 164
108 107 52 105 155 2 19 154 3 206 204 208 207 16 10 166 164
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FLEX 10K Embedded Programmable Logic Family Data Sheet
Table 24. FLEX 10K Device Pin-Outs (Part 2 of 3)
Pin Name 84-Pin PLCC EPF10K10 144-Pin TQFP EPF10K10 EPF10K10A EPF10K20 EPF10K30A
Notes (1), (2)
208-Pin PQFP EPF10K10 EPF10K10A 208-Pin PQFP/ RQFP EPF10K20 EPF10K30 EPF10K30A EPF10K40 240-Pin 240-Pin PQFP/RQFP PQFP/RQFP EPF10K30A EPF10K20 EPF10K100A EPF10K30 EPF10K40 EPF10K50 EPF10K50V EPF10K70
186 185 183 182 181 180 177 4 1 58 59 90, 92, 210, 212 91, 211 209 213 186 185 183 182 181 180 177 4 1 58 59 90, 92, 210, 212 91, 211 209 213
DATA5 (5) DATA4 (5) DATA3 (5) DATA2 (5)
DATA1 (5)
7 8 9 10 11 12 15 74 77 57 56 2, 42, 44, 84 1, 43 3 83
113 112 111 110 109 108 105 4 1 34
162 161 159 158 157 156 153 4 1 50 51 78, 80, 182, 184 79, 183 180 186
162 161 159 158 157 156 153 4 1 50 51 78, 80, 182, 184 79, 183 180 186 6, 23, 35, 43, 76, 77, 106, 109, 117, 137, 145, 181
DATA0 (3), (6) TDI (3) TDO (3) TCK (3) TMS (3) TRST (3) Dedicated Inputs Dedicated Clock Pins DEV_CLRn (4) DEV_OE (4) VCCINT
Note (7)
54, 56, 124, 126 55, 125 122 128
4, 20, 33, 40, 6, 25, 52, 53, 6, 23, 35, 43, 45, 63 75, 93, 123 76, 77, 106, 109, 117, 137, 145, 181
5, 16, 27, 37, 5, 27, 47, 89, 47, 57, 77, 96, 122, 130, 89, 96, 112, 150, 170 122, 130, 140, 150, 160, 170, 189, 205, 224 16, 37, 57, 77, 112, 140, 160, 189, 205, 224
VCCIO
-
5, 24, 45, 61, 5, 22, 34, 42, 71, 94, 115, 66, 84, 98, 134 110, 118, 138, 146, 165, 178, 194
5, 22, 34, 42, - 66, 84, 98, 110, 118, 138, 146, 165, 178, 194
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FLEX 10K Embedded Programmable Logic Family Data Sheet
Table 24. FLEX 10K Device Pin-Outs (Part 3 of 3)
Pin Name 84-Pin PLCC EPF10K10 144-Pin TQFP EPF10K10 EPF10K10A EPF10K20 EPF10K30A
Notes (1), (2)
208-Pin PQFP EPF10K10 EPF10K10A 208-Pin PQFP/ RQFP EPF10K20 EPF10K30 EPF10K30A EPF10K40 240-Pin 240-Pin PQFP/RQFP PQFP/RQFP EPF10K30A EPF10K20 EPF10K100A EPF10K30 EPF10K40 EPF10K50 EPF10K50V EPF10K70
10, 22, 32, 42, 52, 69, 85, 93, 104, 125, 135, 145, 155, 165, 176, 197, 216, 232 -
GNDINT
26, 41, 46, 68, 82
16, 57, 58, 84, 103, 127
21, 33, 49, 21, 33, 49, 10, 22, 32, 81, 82, 123, 81, 82, 123, 42, 52, 69, 129, 151, 185 129, 151, 185 85, 93, 104, 125, 135, 145, 155, 165, 176, 197, 216, 232 20, 32, 48, 59, 72, 91, 124, 130, 152, 171, 188, 201 20, 32, 48, 59, 72, 91, 124, 130, 152, 171, 188, 201 -
GNDIO
-
15, 40, 50, 66, 85, 104, 129, 139
No Connect (N.C.) - (8)
-
7, 8, 9, 14, 15, - 36, 37, 113, 114, 125, 126, 139, 140 134 147
-
-
Total User I/O Pins 59 (9)
102
189
189
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FLEX 10K Embedded Programmable Logic Family Data Sheet
Table 25. FLEX 10K Pin-Outs (Part 1 of 3)
Pin Name 356-Pin BGA EPF10K30
Notes (1), (2)
356-Pin BGA EPF10K50 EPF10K50V EPF10K100A
D4 D3 D24 D2 AC5 AC24 T24 AC2 AC22 AE24 AE23 AD24 AD23 U22 AA24 AF4 AD8 AE5 AD6 AF2 AD5 AD4 AD3 AC3 AC23 AD25 D22 D23 A13, B14, AF14, AE13 A14, AF13 AD13 AE14
403-Pin PGA EPF10K50
503-Pin PGA EPF10K70
MSEL0 (3) MSEL1 (3) nSTATUS (3) nCONFIG (3) DCLK (3) CONF_DONE (3) INIT_DONE (4) nCE (3) nCEO (3) nWS (5) nRS (5) nCS (5) CS (5) RDYnBSY (5) CLKUSR (5) DATA7 (5) DATA6 (5) DATA5 (5) DATA4 (5) DATA3 (5) DATA2 (5) DATA1 (5) DATA0 (3), (6) TDI (3) TDO (3) TCK (3) TMS (3) TRST (3) Dedicated Inputs Dedicated Clock Pins DEV_CLRn (4) DEV_OE (4)
D4 D3 D24 D2 AC5 AC24 T24 AC2 AC22 AE24 AE23 AD24 AD23 U22 AA24 AF4 AD8 AE5 AD6 AF2 AD5 AD4 AD3 AC3 AC23 AD25 D22 D23 A13, B14, AF14, AE13, A14, AF13 AD13 AE14
AN1 AR1 AU37 AU1 E1 C37 R35 G1 E37 E31 A33 A35 C33 N35 G35 C9 A7 E9 C7 A5 E7 C5 C1 J1 G37 A37 AN37 AR37 A17, A21, AU17, AU21 A19, AU19 C17 C19
AT40 AV40 AY4 AY40 H40 F4 V6 K40 H4 A3 C5 C1 C3 T6 H6 E29 D30 C31 B32 D32 B34 E33 F40 M40 K4 D4 AT4 AV4 D20, D24, AY24, AY20 D22, AY22 F22 G21
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FLEX 10K Embedded Programmable Logic Family Data Sheet
Table 25. FLEX 10K Pin-Outs (Part 2 of 3)
Pin Name 356-Pin BGA EPF10K30
Notes (1), (2)
356-Pin BGA EPF10K50 EPF10K50V EPF10K100A
A1, A26, C14, C26, D5, F1, H22, J1, M26, N1, T26, U5, AA1, AD26, AF1, AF26 A7, A23, B4, C15, D25, F4, H24, K5, M23, P2, T25, V2, W22, AB1, AC25, AD18, AF3, AF7, AF16
403-Pin PGA EPF10K50
503-Pin PGA EPF10K70
VCCINT
A1, A26, C14, C26, D5, F1, H22, J1, M26, N1, T26, U5, AA1, AD26, AF1, AF26 A7, A23, B4, C15, D25, F4, H24, K5, M23, P2, T25, V2, W22, AB1, AC25, AD18, AF3, AF7, AF16
B2, D14, E25, F22, K36, T2, T32, V6, AD34, AE5, AL5, AM6, AM20, AN25, AN29, AP4, AT16, AT36 B22, D34, E11, E27, F16, L5, L33, P4, T6, T36, V32, AB36, AG5, AG33, AH2, AM18, AM32, AN11, AN27, AP24, AT22
C11, E39, G27, N5, N41, W39, AC3, AG7, AR3, AR41, AU37, AW5, AW25, AW41, BA17, BA19 C9, C15, C25, C33, C37, E19, E41, G7, L3, R41, U3, U37, W5, AC41, AE5, AJ41, AL39, AU3, AU17, AW3, AW19, BA9, BA27, BA29, BA37 C17, E3, E5, E25, G37, J3, J41, U7, AA3, AE39, AL5, AL41, AU27, AW39, BA7, BA13, BA25
VCCIO
GNDINT
A2, A10, A20, B1, B13, B22, B25, B26, C2, C9, C13, C25, H23, J26, K1, M1, N26, R1, R26, T1, U26, W1, AD2, AD14, AD20, AE1, AE2, AE7, AE25, AE26, AF11, AF19, AF25 -
A2, A10, A20, B1, B13, B22, B25, B26, C2, C9, C13, C25, H23, J26, K1, M1, N26, R1, R26, T1, U26, W1, AD2, AD14, AD20, AE1, AE2, AE7, AE25, AE26, AF11, AF19, AF25 -
B16, B36, D4, E21, F18, F32, G33, P34, U5, Y32, AA33, AB2, AB6, AH36, AM16, AN17, AN21, AP14, AT2
GNDIO
B10, B28, D24, E5, E19, E33, F6, F20, K2, W5, W33, Y6, AB32, AD4, AM22, AN5, AN19, AN33, AP34, AT10, AT28
C21, C23, C39, C41, E13, E31, G3, G17, N3, N39, R3, W41, W3, AA41, AG37, AJ3, AN3, AN41, AU7, AU41, AW13, AW31, BA11, BA21, BA23
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FLEX 10K Embedded Programmable Logic Family Data Sheet
Table 25. FLEX 10K Pin-Outs (Part 3 of 3)
Pin Name 356-Pin BGA EPF10K30
Notes (1), (2)
356-Pin BGA EPF10K50 EPF10K50V EPF10K100A
-
403-Pin PGA EPF10K50
503-Pin PGA EPF10K70
No Connect (N.C.) (10), (11)
C1, D1, D26, E1, E2, - G1, G5, G23, G26, H1, H25, H26, J25, K25, P24, R24, T23, U25, V1, V3, V4, V26, W2, W3, Y1, Y2, Y23, AC26
A19, A21, A23, A31, A33, A35, A39, A41, B16, B18, B22, B24, B30, B40, C29, C35, D18, D26, D28, D38, E27, E37, F18, F2, F26, F30, F32, G23, G25, G29, G31, G33, G35, K6, K42, L39, L43, M2, N7, P38, P4, P42, R37, T40, V42, AC5, AD2, AE3 358
Total User I/O Pins (9)
246
274
310
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Altera Corporation
FLEX 10K Embedded Programmable Logic Family Data Sheet
Table 26. FLEX 10K Pin-Outs (Part 1 of 3)
Pin Name 503-Pin PGA EPF10K100
AT40 AV40 AY4 AY40 H40 F4 V6 K40 H4 A3 C5 C1 C3 T6 H6 E29 D30 C31 B32 D32 B34 E33 F40 M40 K4 D4 AT4 AV4 D20, D24, AY24, AY20 D22, AY22 AV14 AY22 F22 F6
Notes (1), (2)
599-Pin PGA EPF10K130V EPF10K250A
F5 C1 D32 D4 AP1 AM32 AE32 AN2 AP35 AR29 AM28 AL29 AN29 AG35 AM34 AM13 AR12 AN12 AP11 AM11 AR10 AN10 AM4 AN1 AN34 AL31 C35 C34 C18, D18, AM18, AN18 AL18, E18 - - AR17 C3 E43 B4 BE5 BC43 AM40 BB6 BF44 BB40 BA37 AY38 BA39 AW47 AY42 BD14 BA17 BB16 BF12 BG11 BG9 BF10 BC5 BF4 BB42 BE43 F42 B46 B24, C25, BG25, BG23 BF24, A25 - - BE23
600-Pin BGA EPF10K100A
F5 C1 D32 D4
600-Pin BGA EPF10K130V EPF10K250A
MSEL0 (3) MSEL1 (3) nSTATUS (3) nCONFIG (3) DCLK (3) CONF_DONE (3) INIT_DONE (4) nCE (3) nCEO (3) nWS (5) nRS (5) nCS (5) CS (5) RDYnBSY (5) CLKUSR (5) DATA7 (5) DATA6 (5) DATA5 (5) DATA4 (5) DATA3 (5) DATA2 (5) DATA1 (5) DATA0 (3), (6) TDI (3) TDO (3) TCK (3) TMS (3) TRST (3) Dedicated Inputs Dedicated Clock Pins LOCK (12) GCLK1 (13) DEV_CLRn (4)
AP1 AM32 AE32 AN2 AP35 AR29 AM28 AL29 AN29 AG35 AM34 AM13 AR12 AN12 AP11 AM11 AR10 AN10 AM4 AN1 AN34 AL31 C35 C34 C18, D18, AM18, AN18 AL18, E18 - - AR17
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FLEX 10K Embedded Programmable Logic Family Data Sheet
Table 26. FLEX 10K Pin-Outs (Part 2 of 3)
Pin Name 503-Pin PGA EPF10K100
G21 C11, E39, G27, N5, N41, W39, AC3, AG7, AR3, AR41, AU37, AW5, AW25, AW41, BA17, BA19
Notes (1), (2)
599-Pin PGA EPF10K130V EPF10K250A
BC25 E5, A3, A45, C1, C11, C19, C29, C37, C47, G25, L3, L45, W3, W45, AJ3, AJ45, AU3, AU45, BE1, BE11, BE19, BE29, BE37, BE47, BG3, BG45 D24, E9, E15, E21, E27, E33, E39, G7, G41, J5, J43, R5, R43, AA5, AA43, AD4, AD44, AG5, AG43, AN5, AN43, AW5, AW43, BA7, BA41, BC9, BC15, BC21, BC27, BC33, BC39, BD24 - A47, B2, C13, C21, C27, C35, C45, D4, G23, N3, N45, AA3, AA45, AG3, AG45, AR3, AR45, BD44, BE3, BE13, BE21, BE27, BE35, BE45, BG1, BG47 E7, E13, E19, E29, E35, E41, F24, G5, G43, H40, N5, W5, W43, AD6, AD42, AJ5, AJ43, AR5, AR43, AY8, AY40, BA5, BA43, BB24, BC7, BC13, BC19, BC29, BC35, BC41, N43 -
600-Pin BGA EPF10K100A
AR19 AL3, AG5, AE4, AB5, Y2, U3, P5, M2, H1, B1, A11, B18, D24, F31, F35, K32, N34, T35, V32, AA33, AD35, AF32, AK35, AK31, AP24, AR18, AR11, E2, A19 C8, E12, C15, A20, C23, A27, AM26, AR23, AM19, AN15, AL12, AN8, C2, C3, C4, D5, E5, C33, C32, D31, E31, AL5, AM5, AN4, AN3, AM31, AN32, AN33, AP34 - A18, AN35, A1, A2, A3, A4, A5, B2, B3, B4, B5, B6, C5, C6, D6, E6, A31, A32, A33, A34, A35, B31, B32, B33, B34, B35, C30, C31, D30 E30, AL6, AM6, AN5, AN6, AP2, AP3, AP4, AP5, AP6, AR1, AR2, AR3, AR4, AR5, AL30, AM30, AN30, AN31, AP30, AP31, AP32, AP33, AR30, AR31, AR32, AR33, AR34, AR35 -
600-Pin BGA EPF10K130V EPF10K250A
AR19 AL3, AG5, AE4, AB5, Y2, U3, P5, M2, H1, B1, A11, B18, D24, F31, F35, K32, N34, T35, V32, AA33, AD35, AF32, AK35, AK31, AP24, AR18, AR11, E2, A19 C8, E12, C15, A20, C23, A27, AM26, AR23, AM19, AN15, AL12, AN8, C2, C3, C4, D5, E5, C33, C32, D31, E31, AL5, AM5, AN4, AN3, AM31, AN32, AN33, AP34 - A18, AN35, A1, A2, A3, A4, A5, B2, B3, B4, B5, B6, C5, C6, D6, E6, A31, A32, A33, A34, A35, B31, B32, B33, B34, B35, C30, C31, D30 E30, AL6, AM6, AN5, AN6, AP2, AP3, AP4, AP5, AP6, AR1, AR2, AR3, AR4, AR5, AL30, AM30, AN30, AN31, AP30, AP31, AP32, AP33, AR30, AR31, AR32, AR33, AR34, AR35 -
DEV_OE (4) VCCINT
VCCIO
C9, C15, C25, C33, C37, E19, E41, G7, L3, R41, U3, U37, W5, AC41, AE5, AJ41, AL39, AU3, AU17, AW3, AW19, BA9, BA27, BA29, BA37
VCC_CKLK (15) GNDINT
BA19 C17, E3, E5, E25, G37, J3, J41, U7, AA3, AE39, AL5, AL41, AU27, AW39, BA7, BA13, BA25
GNDIO
C21, C23, C39, C41, E13, E31, G3, G17, N3, N39, R3, W3, W41, AA41, AG37, AJ3, AN3, AN41, AU7, AU41, AW13, AW31, BA11, BA23, BA21
VGND_CKLK (15)
BA25
112
Altera Corporation
FLEX 10K Embedded Programmable Logic Family Data Sheet
Table 26. FLEX 10K Pin-Outs (Part 3 of 3)
Pin Name 503-Pin PGA EPF10K100
- -
Notes (1), (2)
599-Pin PGA EPF10K130V EPF10K250A 600-Pin BGA EPF10K100A
AK5, AL4, AM3, AM2, - AM1, AJ5, AL2, AK4, AL1, AK3, AJ4, AH5, AK2, AK1, AJ3, AJ2, G1, G2, G3, F1, F2, H5, G4, F3, E1, E3, F4, G5, D1, D2, D3, E4, E32, D33, D34, D35, G31, F32, E33, E34, E35, F33, G32, H31, F34, G33, G34, G35, AB34, AB33, AB32, AB31, AC35, AC34, AC33, AC32, AC31, AD34, AD33, AD32, AD31, AE35, AE34, AE33 406 470
600-Pin BGA EPF10K130V EPF10K250A
No Connect (N.C.) (14)
Total User I/O Pins 406 (9) Notes to tables:
(1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12)
470
(13) (14) (15)
All pins that are not listed are user I/O pins. Pin-out information on FLEX 10KA devices (except EPF10K50V, EPF10K130V, and EPF10K100A devices) and FLEX 10KB devices are preliminary. Contact Altera Applications for the latest pin-out information. This pin is a dedicated pin; it is not available as a user I/O pin. This pin can be used as a user I/O pin if it is not used for its device-wide or configuration function. This pin can be used as a user I/O pin after configuration. This pin is tri-stated in user mode. The optional JTAG pin TRST is not used in the 144-pin TQFP package. To maintain pin compatibility when transferring to the EPF10K10 device from any other device in the 208-pin PQFP package, do not use these pins as user I/O pins. The user I/O pin count includes dedicated input pins, dedicated clock pins, and all I/O pins. To maintain pin compatibility when transferring to the EPF10K30 device from any other device in the 356-pin BGA package, do not use these pins as user I/O pins. To maintain pin compatibility when transferring from the EPF10K100 to the EPF10K70 in the 503-pin PGA package, do not use these pins as user I/O pins. This pin shows the status of the ClockLock and ClockBoost circuitry. When the ClockLock and ClockBoost circuitry is locked to the incoming clock and generates an internal clock, LOCK is driven high. LOCK remains high if a periodic clock stops clocking. The LOCK function is optional; if the LOCK output is not used, this pin is a user I/O pin. This pin drives the ClockLock and ClockBoost circuitry. To maintain pin compatibility when transferring a to the EPF10K100A device from another device in the 600-pin BGA package, do not use these pin as user I/O pins. This pin is the power or ground for the ClockLock and ClockBoost circuitry. To ensure noise resistance, the power and ground supply to the ClockLock and ClockBoost circuitry should be isolated from the power and ground to the rest of the device.
Altera Corporation
113
FLEX 10K Embedded Programmable Logic Family Data Sheet
Revision History
The information contained in the FLEX 10K Programmable Logic Family Data Sheet version 3.10 supersedes information published in previous versions.
Version 3.10 Changes
The FLEX 10K Programmable Logic Family Data Sheet version 3.10 contains the following changes:
s s s s s s
s s
All references to FLEX 10KB devices were deleted. Information on PCI clamping diode was added. Information on ByteBlasterMV parallel port download cable was added. Timing information for EPF10K50V, EPF10K70, and EPF10K100A devices was revised. K constant values in the Power Consumption section was updated. ICCACTIVE vs. Operating Frequency graphs for EPF10K30A, EPF10K100B, and EPF10K250A devices were added to Figure 29. MultiVolt I/O interface section was updated. VCCINT and VCCIO pins of the 240-pin PQFO/RQFP package for EPF10K30A and EPF10K100A devices were revised in Table 24.
(R)
2610 Orchard Parkway San Jose, CA 95134-2020 (408) 894-7000 Applications Hotline: (800) 800-EPLD Customer Marketing: (408) 894-7104 Literature Services: (408) 894-7144 114
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Altera, MAX, MAX+PLUS, MAX+PLUS II, AHDL, FLEX 10K, FLEX 10KA, FLEX 10KE, MultiVolt, BitBlaster, ByteBlaster, ByteBlasterMV, EPF10K10, EPF10K20, EPF10K30, EPF10K30A, EPF10K40, EPF10K50, EPF10K50V, EPF10K70, EPF10K100, EPF10K100A, EPF10K130V, EPF10K250A, EPF10K100B, Clocklock, Clockboost, and FastTrack Interconnect. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with AlteraOs standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. Copyright (c) 1996 Altera Corporation. All rights reserved.
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